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公开(公告)号：US20140282295A1
公开(公告)日：2014-09-18
申请号：US13802833
申请日：2013-03-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Hsien Huang , Ming-Jui Chen , Ching-Chun Huang , Chia-Wei Huang , Yu-Feng Chao , Yu-Chuan Chang
IPC: G06F17/50
CPC classification number: H01L21/76816 , G03F1/36 , H01L21/76807
Abstract: The present invention provides a method for forming at least a photo mask. A first photo-mask pattern relating to a first structure is provides. A second photo-mask pattern relating to a second structure is provides. A third photo-mask pattern relating to a third structure is provides. The first structure, the second structure and the third structure are disposed in a semiconductor structure in sequence. An optical proximity process including a comparison step is provided, wherein the comparison step includes comparing the first photo-mask pattern and the third photo-mask pattern. Last, the first photo-mask pattern is import to form a first mask, the second photo-mask pattern is import to form a second mask, and the third photo-mask pattern is import to form a third mask. The present invention further provides an OPC method.
Abstract translation: 本发明提供一种至少形成光掩模的方法。 提供与第一结构相关的第一光掩模图案。 提供与第二结构相关的第二光掩模图案。 提供了与第三结构相关的第三光掩模图案。 第一结构，第二结构和第三结构依次设置在半导体结构中。 提供了包括比较步骤的光学邻近处理，其中比较步骤包括比较第一光掩模图案和第三光掩模图案。 最后，导入第一光掩模图案以形成第一掩模，第二光掩模图案被导入以形成第二掩模，并且导入第三光掩模图案以形成第三掩模。 本发明还提供一种OPC方法。
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公开(公告)号：US12224001B2
公开(公告)日：2025-02-11
申请号：US18071658
申请日：2022-11-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Hsien Huang , Yu-Tse Kuo , Shu-Ru Wang , Li-Ping Huang , Yu-Fang Chen , Chun-Yen Tseng , Tzu-Feng Chang , Chun-Chieh Chang
IPC: G11C11/412 , H01L29/66 , H01L29/78 , H10B10/00
Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.
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公开(公告)号：US20240404587A1
公开(公告)日：2024-12-05
申请号：US18218025
申请日：2023-07-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Hsien Huang , Yu-Tse Kuo , Shu-Ru Wang , Li-Ping Huang , Chun-Yen Tseng
IPC: G11C11/412 , G11C5/06
Abstract: The invention provides a layout pattern of static random access memory (SRAM), which comprises a substrate, and a plurality of fin structures and a plurality of gate structures are located on the substrate to form a plurality of transistors. The plurality of transistors comprise a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1A), a second access transistor (PG1B), a third access transistor (PG2A) and a fourth access transistor (PG2B). A first word line contact pad connected to a gate of the first access transistor (PG1A) and a first word line, and a second word line contact pad connected to a gate of the second access transistor (PG1B) and a second word line, the first word line contact pad and the second word line contact pad do not overlap in a vertical direction.
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公开(公告)号：US12148809B2
公开(公告)日：2024-11-19
申请号：US17583225
申请日：2022-01-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Hsien Huang , Yu-Tse Kuo , Shu-Ru Wang , Chien-Hung Chen , Li-Ping Huang , Chun-Yen Tseng
IPC: H01L29/423 , G11C5/06 , G11C11/412 , H01L29/78 , H10B10/00
Abstract: The present invention provides a layout pattern of static random access memory, comprising a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.
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公开(公告)号：US20230403837A1
公开(公告)日：2023-12-14
申请号：US17857065
申请日：2022-07-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Hsien Huang , Yu-Tse Kuo , Shu-Ru Wang , Li-Ping Huang , Chun-Yen Tseng
IPC: H01L27/11
CPC classification number: H01L27/1104
Abstract: The invention provides a static random access memory (SRAM) array pattern, which comprises a substrate, a first region, a second region, a third region and a fourth region are defined on the substrate and arranged in an array, each region partially overlaps with the other three regions, and each region contains a SRAM cell, the layout of the SRAM cell in the first region is the same as that in the third region, the layout of the SRAM cell in the second region is the same as that in the fourth region, and the layout of the SRAM cell in the first region and the layout of the SRAM cell in the fourth region are mirror patterns along a horizontal axis.
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公开(公告)号：US20230018513A1
公开(公告)日：2023-01-19
申请号：US17952327
申请日：2022-09-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Yen Tseng , Shu-Ru Wang , Yu-Tse Kuo , Chang-Hung Chen , Yi-Ting Wu , Shu-Wei Yeh , Ya-Lan Chiou , Chun-Hsien Huang
Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region and a second cell region and a diffusion region on the substrate extending through the first cell region and the second cell region. Preferably, the diffusion region includes a first H-shape and a second H-shape according to a top view.
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公开(公告)号：US20210118507A1
公开(公告)日：2021-04-22
申请号：US17114373
申请日：2020-12-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Hsien Huang , Ching-Cheng Lung , Yu-Tse Kuo , Shu-Ru Wang , Chun-Yen Tseng
Abstract: A layout pattern of a two-port ternary content addressable memory (TCAM) includes a first storage unit, a second storage unit, a first comparison circuit and a second comparison circuit. The first comparison circuit and the second comparison circuit are positioned in a first side area of a side and a second side area of another side of the layout pattern, respectively. The first storage unit and the second storage unit are positioned in a first middle area and a second middle area between the first side area and the second side area, respectively. The first storage unit is connected to the first comparison circuit through a first gate structure and connected to the second comparison circuit through a second gate structure. The second storage unit is connected to the first comparison circuit through a third gate structure and connected to the second comparison circuit through a fourth gate structure.
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公开(公告)号：US10706914B2
公开(公告)日：2020-07-07
申请号：US16019521
申请日：2018-06-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Yen Tseng , Ching-Cheng Lung , Yu-Tse Kuo , Chun-Hsien Huang , Hsin-Chih Yu , Shu-Ru Wang
IPC: G11C11/00 , G11C11/412 , G11C11/419 , H01L43/08 , G11C7/12 , H01L27/11 , H01L43/02 , H01L43/10 , G01R33/09 , G11C8/08
Abstract: A static random access memory (SRAM) structure includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, a second inverter comprising a second pull-up transistor and a second pull-down transistor, a first pass transistor coupled to the first inverter, and a second pass transistor coupled to the second inverter. Preferably, the first inverter is coupled to a first tunnel magnetoresistance (TMR) structure and the second inverter is coupled to a second TMR structure.
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公开(公告)号：US20200083232A1
公开(公告)日：2020-03-12
申请号：US16152423
申请日：2018-10-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Hsien Huang , Ching-Cheng Lung , Yu-Tse Kuo , Shu-Ru Wang , Chun-Yen Tseng
Abstract: A layout pattern of a static random access memory (SRAM) preferably includes a first inverter and a second inverter. Preferably, the first inverter includes a first gate structure extending along a first direction on a substrate, in which the first gate structure includes a gate of a first pull-up device (PL1) and a gate of a first pull-down device (PD1). The second inverter includes a second gate structure extending along the first direction on the substrate, in which the second gate structure includes a gate of a second pull-up device (PL2) and a gate of a second pull-down device (PD2) and the gate of the PD1 is directly under the gate of the PD2.
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公开(公告)号：US20190362776A1
公开(公告)日：2019-11-28
申请号：US16019521
申请日：2018-06-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Yen Tseng , Ching-Cheng Lung , Yu-Tse Kuo , Chun-Hsien Huang , Hsin-Chih Yu , Shu-Ru Wang
IPC: G11C11/412 , G11C11/419 , H01L43/08 , G11C7/12 , G11C8/08 , H01L43/02 , H01L43/10 , G01R33/09 , H01L27/11
Abstract: A static random access memory (SRAM) structure includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, a second inverter comprising a second pull-up transistor and a second pull-down transistor, a first pass transistor coupled to the first inverter, and a second pass transistor coupled to the second inverter. Preferably, the first inverter is coupled to a first tunnel magnetoresistance (TMR) structure and the second inverter is coupled to a second TMR structure.
