公开(公告)号：US10170481B2

公开(公告)日：2019-01-01

申请号：US15915026

申请日：2018-03-07

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Li-Wei Feng ,  Chien-Ting Ho ,  Tsung-Ying Tsai

IPC: H01L27/108 ,  H01L21/762 ,  H01L29/06

Abstract: A semiconductor memory device and a method of forming the same, the semiconductor memory device includes a substrate, a plurality of bit lines, a gate, a spacer layer and a first spacer. The substrate has a memory cell region and a periphery region, the a plurality of bit lines are disposed on the substrate, within the memory cell region, and the gate is disposed on the substrate, within the periphery. The spacer layer covers the bit lines and a sidewall of the gate. The first spacer is disposed at two sides of the gate, covers on the spacer layer.

公开(公告)号：US10169521B2

公开(公告)日：2019-01-01

申请号：US15479271

申请日：2017-04-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Yu-Cheng Tung ,  Chien-Ting Ho ,  Li-Wei Feng ,  Emily SH Huang

IPC: G06F17/00 ,  G06F17/50 ,  H01L27/02 ,  H01L27/108

Abstract: A method for forming a contact plug layout include following steps. (a) Receiving a plurality of active region patterns and a plurality of buried gate patterns that are parallel with each other, and each active region pattern overlaps two buried gate patterns to form two overlapping regions and one contact plug region in between the two overlapping regions in each active region pattern; and (b) forming a contact plug pattern in each contact plug region, the contact plug pattern respectively includes a parallelogram, and an included angle of the parallelogram is not equal to 90°. The contact plug pattern in each active region pattern partially overlaps the two buried gate pattern, respectively. The step (a) to the step (b) are implemented using a computer.

公开(公告)号：US20180323190A1

公开(公告)日：2018-11-08

申请号：US15610642

申请日：2017-06-01

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Chien-Ting Ho ,  Shih-Fang Tzou

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/823456 ,  H01L21/823481 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/66666

Abstract: A method for fabricating semiconductor device includes the steps of first forming a first trench and a second trench in a substrate and then forming a shallow trench isolation (STI) in the first trench, in which the STI comprises a top portion and a bottom portion and a top surface of the top portion is even with or higher than a bottom surface of the second trench. Next, a conductive layer is formed in the first trench and the second trench to form a first gate structure and a second gate structure.

公开(公告)号：US20180190664A1

公开(公告)日：2018-07-05

申请号：US15856022

申请日：2017-12-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chien-Cheng Tsai ,  Feng-Ming Huang ,  Ying-Chiao Wang ,  Chien-Ting Ho ,  Li-Wei Feng ,  Tsung-Ying Tsai

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L27/10894 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/3065 ,  H01L21/3081 ,  H01L27/10823 ,  H01L27/10876

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first buried gate and a second buried gate in the substrate on the memory region; forming a first silicon layer on the substrate on the periphery region; forming a stacked layer on the first silicon layer; forming an epitaxial layer on the substrate between the first buried gate and the second buried gate; and forming a second silicon layer on the epitaxial layer on the memory region and the stacked layer on the periphery region.

公开(公告)号：US09985035B1

公开(公告)日：2018-05-29

申请号：US15820455

申请日：2017-11-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Chien-Ting Ho ,  Yu-Cheng Tung

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10885 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/1085 ,  H01L27/10855 ,  H01L27/10894 ,  H01L27/10897

Abstract: A semiconductor memory structure includes a substrate including a memory cell region and a cell edge region adjacent to the memory cell region. Active regions are formed in the substrate and in the memory cell region and the cell edge region. At least a dummy bit line is formed on the active regions in the cell edge region. The dummy bit line extends along a first direction and overlaps at least two active regions along a second direction. The dummy bit line further includes a first inner line portion and an outer line portion. The first inner line portion and the outer line portion extend along the first direction and a width of the first inner line portion is different from a width of the outer line portion.

公开(公告)号：US09929162B1

公开(公告)日：2018-03-27

申请号：US15456564

申请日：2017-03-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ying-Chiao Wang ,  Yu-Chieh Lin ,  Chien-Ting Ho

IPC: H01L27/10 ,  H01L27/108

CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

Abstract: A semiconductor device include a substrate including at least a memory cell region formed thereon, an isolation mesh formed on the substrate; and a plurality of storage node contact plugs. The semiconductor device includes a plurality of memory cells formed in the memory cell region. The isolation mesh includes a plurality of essentially homogeneous dielectric sidewalls and a plurality of first apertures defined by the dielectric sidewalls. The storage node contact plugs are respectively formed in the first apertures, and electrically connected to the memory cells respectively.

公开(公告)号：US09859283B1

公开(公告)日：2018-01-02

申请号：US15479290

申请日：2017-04-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Chien-Ting Ho ,  Yu-Cheng Tung

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10885 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/1085 ,  H01L27/10855 ,  H01L27/10894 ,  H01L27/10897

Abstract: A semiconductor memory structure includes a substrate including a memory cell region, a peripheral circuit region and a cell edge region defined thereon, and the cell edge region is defined in between the memory cell region and the peripheral circuit region. The semiconductor memory structure includes a plurality of active regions formed in the memory cell region, the cell edge region and the peripheral circuit region, and at least a dummy bit line formed on the active regions in the cell edge region. The dummy bit line is extended along a first direction and overlaps at least two active regions in a second direction. And the first direction and the second direction are perpendicular to each other. The dummy bit line includes a first inner line portion and an outer line portion, and the first inner line portion and the outer line portion include different widths and different spacers.

公开(公告)号：US09679901B1

公开(公告)日：2017-06-13

申请号：US15296955

申请日：2016-10-18

Applicant: United Microelectronics Corp. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Chien-Ting Ho ,  Le-Tien Jung ,  Shih-Fang Tzou ,  Chin-Lung Lin ,  Harn-Jiunn Wang

IPC: H01L21/762 ,  H01L27/108 ,  H01L29/06 ,  H01L21/461

CPC classification number: H01L27/10894 ,  H01L21/461 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/0649

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a plurality of active areas, and an isolation structure. The substrate has a device region and a peripheral region surrounding the device region. The active areas are located in the substrate in the device region. When viewed from above, the edges of the ends of the active areas adjacent to the boundary of the device region are aligned with each other, and the width of the ends of the active areas adjacent to the boundary of the device region is greater than the width of the other portions of the active areas. The isolation structure is disposed in the substrate and surrounds the active areas and is located in the peripheral region.

公开(公告)号：US11563012B2

公开(公告)日：2023-01-24

申请号：US17324114

申请日：2021-05-19

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Shih-Fang Tzou ,  Chien-Ting Ho ,  Ying-Chiao Wang ,  Yu-Ching Chen ,  Hui-Ling Chuang ,  Kuei-Hsuan Yu

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/762

Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

公开(公告)号：US10672864B2

公开(公告)日：2020-06-02

申请号：US16297733

申请日：2019-03-11

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Chin Wu ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Jui-Min Lee ,  Po-Chun Chen ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Wen-Chieh Lu ,  Chien-Ting Ho ,  Tsung-Ying Tsai ,  Kai-Ping Chen

IPC: H01L49/02 ,  H01L29/94 ,  H01L27/108

Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.