公开(公告)号：US10782909B2

公开(公告)日：2020-09-22

申请号：US15984611

申请日：2018-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Hwa Kim ,  Sehwan Lee

IPC: G06F3/06

Abstract: The data storage device including a buffer configured to receive first information including first data and a first stream class number identifying characteristics of the first data and second information including second data and a second stream class number identifying characteristics of the second data and store the first and second information therein, the second stream class number being different from the first stream class number, a non-volatile memory including a shared memory area and a dedicated memory area different from the shared memory area and configured to store the first and second data stored in the buffer, the non-volatile memory, and a controller configured to control the buffer and the non-volatile memory, the controller configured to store the first and second data stored in the shared memory area, and then migrate the first data stored in the shared memory area to the dedicated memory area may be provided.

公开(公告)号：US20200026978A1

公开(公告)日：2020-01-23

申请号：US16552619

申请日：2019-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilia Ovsiannikov ,  Ali Shafiee Ardestani ,  Joseph H. Hassoun ,  Lei Wang ,  Sehwan Lee ,  JoonHo Song ,  Jun-Woo Jang ,  Yibing Michelle Wang ,  Yuecheng Li

IPC: G06N3/04 ,  G06F17/16 ,  G06N3/08

Abstract: A neural processor. In some embodiments, the processor includes a first tile, a second tile, a memory, and a bus. The bus may be connected to the memory, the first tile, and the second tile. The first tile may include: a first weight register, a second weight register, an activations buffer, a first multiplier, and a second multiplier. The activations buffer may be configured to include: a first queue connected to the first multiplier and a second queue connected to the second multiplier. The first queue may include a first register and a second register adjacent to the first register, the first register being an output register of the first queue. The first tile may be configured: in a first state: to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and in a second state: to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue.