公开(公告)号：US20250165362A1

公开(公告)日：2025-05-22

申请号：US18513380

申请日：2023-11-17

Applicant: STMicroelectronics International N.V.

Inventor： Antonio DE VITA ,  David SIORPAES ,  Thomas BOESCH ,  Giuseppe DESOLI

IPC: G06F11/22

Abstract: A hardware accelerator includes a plurality of functional circuits, a stream switch, a plurality of direct memory access (DMA) channels coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits, and a debug and trace unit coupled to the stream switch, wherein in operation, the debug and trace unit monitors a set of data signals to and from the stream switch via wired probes and implements one or more event counters, one or more triggers, and one or more tracers using components internal to the hardware accelerator including one or more registers of the hardware accelerator, and wherein the one or more tracers output trace data packets via the stream switch.

公开(公告)号：US20240281397A1

公开(公告)日：2024-08-22

申请号：US18192631

申请日：2023-03-29

Applicant: STMicroelectronics International N.V.

Inventor： Michele ROSSI ,  Giuseppe DESOLI ,  Thomas BOESCH

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4022 ,  G06F13/1668

Abstract: A hardware accelerator includes processing elements of a neural network, each processing element having a memory; a stream switch; stream engines coupled to functional circuits via the stream switch, wherein the stream engines, in operation, generate data streaming requests to stream data to and from functional circuits of the plurality of functional circuits; a first system bus interface coupled to the stream engines; a second system bus interface coupled to the processing elements; and mode control circuitry, which, in operation, sets respective modes of operation for the plurality of processing elements. The modes of operation include: a compute mode of operation in which the processing element performs computing operations using the memory associated with the processing element; and a memory mode of operation in which the memory associated with the processing element performs memory operations, bypassing the stream switch, via the second system bus interface.