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公开(公告)号：US20220351759A1
公开(公告)日：2022-11-03
申请号：US17306562
申请日：2021-05-03
Applicant: Micron Technology, Inc.
Inventor： Karthik Sarpatwari , Nevil N. Gajera , Jessica Chen , Lingming Yang
IPC: G11C7/10
Abstract: Methods, systems, and devices for dynamic read voltage techniques are described. In some examples, a memory device may include one or more partitions made up of multiple disjoint subsets of memory arrays. The memory device may receive a read command to read the one or more partitions and enter a drift determination phase. During the drift determination phase, the memory device may concurrently apply a respective voltage of a set of voltages to each disjoint subset and determine a quantity of memory cells in each disjoint subset that have a threshold voltage below the applied voltage. Based on a comparison between the determined quantity of memory cells and a predetermined quantity of memory cells, the memory device may select a voltage from the set of voltages and utilize the selected voltage to read the one or more partitions.
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公开(公告)号：US20220319587A1
公开(公告)日：2022-10-06
申请号：US17221417
申请日：2021-04-02
Applicant: Micron Technology, Inc.
Inventor： Karthik Sarpatwari , Fabio Pellizzer , Nevil N. Gajera
Abstract: Systems, methods and apparatus to determine a programming mode of a set of memory cells without having bit values stored in the memory cells to include an identifier of the programming mode. During the test of which of the memory cells in the set is in a lowest voltage region, which is a common operation for reading the memory cells programmed in different mode, the statistics of the memory cells found to be in the lowest voltage region can be compared to the known, different behaviors of the memory cell set programmed in different modes. A match with the behavior of one of the modes can be used to identify the matching mode as the programming mode of the set of memory cells.
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公开(公告)号：US20220223212A1
公开(公告)日：2022-07-14
申请号：US17709102
申请日：2022-03-30
Applicant: Micron Technology, Inc.
Inventor： Karthik Sarpatwari , Nevil N. Gajera
Abstract: The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of four possible data states by applying a first voltage pulse to the memory cell wherein the first voltage pulse has a first polarity and a first magnitude, and applying a second voltage pulse to the memory cell wherein the second voltage pulse has a second polarity and a second magnitude, and the second voltage pulse is applied for a shorter duration than the first voltage pulse.
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公开(公告)号：US11295822B2
公开(公告)日：2022-04-05
申请号：US16993831
申请日：2020-08-14
Applicant: Micron Technology, Inc.
Inventor： Karthik Sarpatwari , Nevil N. Gajera
Abstract: The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of four possible data states by applying a first voltage pulse to the memory cell wherein the first voltage pulse has a first polarity and a first magnitude, and applying a second voltage pulse to the memory cell wherein the second voltage pulse has a second polarity and a second magnitude, and the second voltage pulse is applied for a shorter duration than the first voltage pulse.
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公开(公告)号：US20250014641A1
公开(公告)日：2025-01-09
申请号：US18890624
申请日：2024-09-19
Applicant: Micron Technology, Inc.
Inventor： Yen Chun Lee , Nevil N. Gajera , Karthik Sarpatwari
IPC: G11C13/00
Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device applies multiple pre-read voltages to memory cells prior to performing write operations on the memory cells. The controller applies a first pre-read voltage to determine which of the memory cells have a sensed current that exceeds a threshold. In response to determining that a percentage of the memory cells exceeding the threshold is too low (e.g., below a fixed limit), the controller determines to apply a second pre-read voltage to the memory cells. The second pre-read voltage has a greater magnitude than the first pre-read voltage, and can be applied to ensure greater reliability in properly determining the existing programming state of the memory cells. The controller then applies write voltages to the memory cells as appropriate based on target logic states for each memory cell and the programming mode to be used by the controller.
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公开(公告)号：US20240339433A1
公开(公告)日：2024-10-10
申请号：US18610268
申请日：2024-03-20
Applicant: Micron Technology, Inc.
Inventor： Bharat Bhushan , Nevil N. Gajera , Akshay N. Singh , Kunal R. Parekh
CPC classification number: H01L25/0652 , H01L23/31 , H01L23/481 , H01L24/08 , H01L24/19 , H01L24/20 , H01L24/80 , H01L24/94 , H01L25/50 , H10B80/00 , H01L2224/08145 , H01L2224/19 , H01L2224/21 , H01L2224/80895 , H01L2224/80896 , H01L2224/94 , H01L2225/06548
Abstract: A semiconductor device with a through dielectric via is disclosed. The semiconductor device assembly can include a semiconductor die and multiple stacks of semiconductor dies coupled with the semiconductor die at different lateral locations. Dielectric material can be disposed at the semiconductor die between the multiple stacks of semiconductor dies. The through dielectric via can extend entirely through the dielectric material to the semiconductor die such that the through dielectric via couples with circuitry at the semiconductor die. In this way, the through dielectric via can provide power to the semiconductor die (e.g., exclusive of the multiple stacks of semiconductor dies).
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公开(公告)号：US11942139B2
公开(公告)日：2024-03-26
申请号：US18075570
申请日：2022-12-06
Applicant: Micron Technology, Inc.
Inventor： Karthik Sarpatwari , Lingming Yang , Nevil N. Gajera , John Christopher M. Sancon
IPC: G11C11/406 , G11C11/4074 , G11C11/4091
CPC classification number: G11C11/40622 , G11C11/40615 , G11C11/4074 , G11C11/4091
Abstract: The present disclosure includes apparatuses, methods, and systems for performing refresh operations on memory cells. An embodiment includes a memory having a group of memory cells and one or more additional memory cells whose data state is indicative of whether to refresh the group of memory cells, and circuitry configured to apply a first voltage pulse to the group of memory cells to sense a data state of the memory cells of the group, apply, while the first voltage pulse is applied to the group of memory cells, a second voltage pulse having a greater magnitude than the first voltage pulse to the one or more additional memory cells to sense a data state of the one or more additional memory cells, and determine whether to perform a refresh operation on the group of memory cells based on the sensed data state of the one or more additional memory cells.
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公开(公告)号：US11710528B2
公开(公告)日：2023-07-25
申请号：US17487792
申请日：2021-09-28
Applicant: Micron Technology, Inc.
Inventor： Karthik Sarpatwari , Nevil N. Gajera , Hongmei Wang , Mingdong Cui
CPC classification number: G11C16/3404 , G11C16/10 , G11C16/26 , G11C16/30
Abstract: Methods, systems, and devices for data-based polarity write operations are described. A write command may cause a set of data to be written to a set of memory cells. To write the set of data, a write operation that applies voltages across the memory cells based on a logic state of data to be written to the memory cells may be used. During a first interval of the write operation, a voltage may be applied across a memory cell based on a logic state of a data bit to be written to the memory cell. During a second interval of the write operation, a voltage may be applied across the memory cell based on an amount of charge conducted by the memory cell during the first interval.
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公开(公告)号：US11688460B2
公开(公告)日：2023-06-27
申请号：US17491070
申请日：2021-09-30
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Nevil N. Gajera , John Frederic Schreck
IPC: G11C13/00
CPC classification number: G11C13/0026 , G11C13/003 , G11C13/0004 , G11C13/0028
Abstract: As described, an apparatus may include a memory cell corresponding to a memory address and an access line forming at least a portion of the memory cell. The apparatus may include a first decoder associated with a first delivery driver coupled to a first end of the access line and a second decoder associated with a second delivery driver coupled to another end of the access line.
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公开(公告)号：US11664074B2
公开(公告)日：2023-05-30
申请号：US17336913
申请日：2021-06-02
Applicant: Micron Technology, Inc.
Inventor： Karthik Sarpatwari , Nevil N. Gajera , Lingming Yang , Yen Chun Lee , Jessica Chen , Francesco Douglas Verna-Ketel
CPC classification number: G11C16/10 , G11C16/08 , G11C16/24 , G11C16/0483
Abstract: Systems, methods and apparatus to program memory cells to an intermediate state. A first voltage pulse is applied in a first polarity across each respective memory cell among the memory cells to move its threshold voltage in the first polarity to a first voltage region representative of a first value. A second voltage pulse is then applied in a second polarity to further move its threshold voltage in the first polarity to a second voltage region representative of a second value and the intermediate state. A magnitude of the second voltage pulse applied for the memory cells is controlled by increasing the magnitude in increments until the memory cells are sensed to be conductive. Optionally, prior to the first voltage pulse, a third voltage pulse is applied in the second polarity to cancel or reduce a drift in threshold voltages of the respective memory cell.
