公开(公告)号：US20190140954A1

公开(公告)日：2019-05-09

申请号：US15805762

申请日：2017-11-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Alan Dodson Smith ,  Chintan S. Patel ,  Eric Christopher Morton ,  Vydhyanathan Kalyanasundharam ,  Narendra Kamat

IPC: H04L12/803 ,  H04L12/935 ,  H04L12/825

Abstract: A system for implementing load balancing schemes includes one or more processing units, a memory, and a communication fabric with a plurality of switches coupled to the processing unit(s) and the memory. A switch of the fabric determines a first number of streams on a first input port that are targeting a first output port. The switch also determines a second number of requestors, from all input ports, that are targeting the first output port. Then, the switch calculates a throttle factor for the first input port by dividing the first number of streams by the second number of streams. The switch applies the throttle factor to regulate bandwidth on the first input port for requestors targeting the first output port. The switch also calculates throttle factors for the other ports and applies the throttle factors when regulating bandwidth on the other ports.

公开(公告)号：US20170371787A1

公开(公告)日：2017-12-28

申请号：US15192734

申请日：2016-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Eric Christopher Morton ,  Amit P. Apte ,  Elizabeth M. Cooper

IPC: G06F12/0815 ,  G06F12/0813

CPC classification number: G06F12/0815 ,  G06F9/526 ,  G06F12/0813 ,  G06F12/0828 ,  G06F12/0842 ,  G06F2209/522 ,  G06F2209/523 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/154 ,  G06F2212/284 ,  G06F2212/608 ,  G06F2212/62

Abstract: A system and method for network traffic management between multiple nodes are described. A computing system includes multiple nodes connected to one another. When a home node determines a number of nodes requesting read access for a given data block assigned to the home node exceeds a threshold and a copy of the given data block is already stored at a first node of the multiple nodes in the system, the home node sends a command to the first node. The command directs the first node to forward a copy of the given data block to the home node. The home node then maintains a copy of the given data block and forwards copies of the given data block to other requesting nodes until the home node detects a write request or a lock release request for the given data block.

公开(公告)号：US09354970B2

公开(公告)日：2016-05-31

申请号：US14230115

申请日：2014-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Ross V. La Fetra ,  Vilas K. Sridharan ,  Vydhyanathan Kalyanasundharam ,  Dean A. Liberty ,  Amit P. Apte

IPC: G06F11/10 ,  H04L1/00 ,  H04L27/00 ,  G11B20/18 ,  G11C29/52

CPC classification number: G06F11/1076 ,  G06F11/10 ,  G11B20/1833 ,  G11C29/52 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0071 ,  H04L2027/0036

Abstract: A method and device are described for encoding erroneous data in an error correction code (ECC) protected memory. In one embodiment, incoming data including a plurality of data symbols and a data integrity marker is received. At least one extra symbol is used to mark the incoming data as error-free data or erroneous data (i.e., poison) based on the data integrity marker. ECC may be created to protect the data symbols. The ECC may include a plurality of check symbols, a plurality of unused symbols and the at least one extra symbol. In another embodiment, an error marker may be propagated from a single ECC word to all ECC words of data block (e.g., a cache line, a page, and the like) to prevent errors due to corruption of the error marker caused by faulty memory in the erroneous ECC word.

Abstract translation: 描述了用于对纠错码（ECC）保护存储器中的错误数据进行编码的方法和装置。 在一个实施例中，接收包括多个数据符号和数据完整性标记的输入数据。 使用至少一个额外的符号来将输入数据标记为基于数据完整性标记的无错误数据或错误数据（即毒药）。 可以创建ECC以保护数据符号。 ECC可以包括多个检查符号，多个未使用的符号和至少一个额外的符号。 在另一个实施例中，错误标记可以从单个ECC字传播到数据块的所有ECC字（例如，高速缓存线，页等），以防止由故障存储器引起的错误标记的损坏引起的错误 在错误的ECC字中。

公开(公告)号：US20160117248A1

公开(公告)日：2016-04-28

申请号：US14523045

申请日：2014-10-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Eric Morton ,  Patrick Conway ,  Elizabeth Morrow Cooper ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/08 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F12/0815 ,  G06F11/3037 ,  G06F11/3409 ,  G06F2212/604 ,  Y02D10/13

Abstract: A processor includes a set of processing modules, each of the processing modules including a cache and a coherency manager that keeps track of the memory addresses of data stored at the caches of other processing modules. In response to its local cache requesting access to a particular memory address or other triggering event, the coherency manager generates a coherency probe. In the event that the generated coherency probe is targeted to multiple processing modules, the coherency manager includes a set of multicast bits indicating the processing modules whose caches include copies of the data targeted by the multicast probe. A transport switch that connects the processing module to the fabric communicates the coherency probe only to subset of processing modules indicated by the multicast bits.

Abstract translation: 处理器包括一组处理模块，每个处理模块包括高速缓存和一致性管理器，其跟踪存储在其他处理模块的高速缓存处的数据的存储器地址。 响应于其本地缓存请求访问特定存储器地址或其他触发事件，相关性管理器生成一致性探测器。 在生成的一致性探测针对多个处理模块的情况下，相关性管理器包括指示处理模块的一组多播位，其高速缓存包括多播探测器所针对的数据的副本。 将处理模块连接到结构的传输交换机仅将一致性探测器传送到由多播位指示的处理模块的子集。

公开(公告)号：US20150089168A1

公开(公告)日：2015-03-26

申请号：US14032887

申请日：2013-09-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Kevin M. Brandl ,  Adnan Dhanani

IPC: G06F12/06

CPC classification number: G06F12/0607

Abstract: A system and method for mapping an address space to a non-power-of-two number of memory channels. Addresses are translated and interleaved to the memory channels such that each memory channel has an equal amount of mapped address space. The address space is partitioned into two regions, and a first translation function is used for memory requests targeting the first region and a second translation function is used for memory requests targeting the second region. The first translation function is based on a first set of address bits and the second translation function is based on a second set of address bits.

Abstract translation: 一种用于将地址空间映射到非功率数量的存储器通道的系统和方法。 地址被转换并交错到存储器通道，使得每个存储器通道具有相等量的映射地址空间。 地址空间被划分成两个区域，并且第一翻译函数用于针对第一区域的存储器请求，并且第二翻译函数用于针对第二区域的存储器请求。 第一翻译函数基于第一组地址位，第二翻译函数基于第二组地址位。

公开(公告)号：US12105952B2

公开(公告)日：2024-10-01

申请号：US17957469

申请日：2022-09-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Vydhyanathan Kalyanasundharam

IPC: G06F3/06

CPC classification number: G06F3/0607 ,  G06F3/0629 ,  G06F3/067

Abstract: Systems, methods, and techniques are provided for a fabric addressable memory. A memory access request is received from a host computing device attached via one edge port of one or more interconnect switches, the memory access request directed to a destination segment of a physical fabric memory block that is allocated in local physical memory of the host computing device. The edge port accesses a stored mapping between segments of the physical fabric memory block and one or more destination port identifiers that are each associated with a respective edge port of the fabric addressable memory. The memory access request is routed by the one edge port to a destination edge port based on the stored mapping.

公开(公告)号：US12093181B2

公开(公告)日：2024-09-17

申请号：US17852296

申请日：2022-06-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Chintan S. Patel ,  Alexander J. Branover ,  Benjamin Tsien ,  Edgar Munoz ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0864 ,  G06F12/0871

CPC classification number: G06F12/0871 ,  G06F12/0811 ,  G06F12/0864

Abstract: A technique for operating a cache is disclosed. The technique includes based on a workload change, identifying a first allocation permissions policy; operating the cache according to the first allocation permissions policy; based on set sampling, identifying a second allocation permissions policy; and operating the cache according to the second allocation permissions policy.

公开(公告)号：US20240220409A1

公开(公告)日：2024-07-04

申请号：US18090249

申请日：2022-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Alan D. Smith ,  Chintan S. Patel ,  William L. Walker

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/1024

Abstract: The disclosed computer-implemented method includes partitioning a cache structure into a plurality of cache partitions designated by a plurality of cache types, forwarding a memory request to a cache partition corresponding to a target cache type of the memory request, and performing, using the cache partition, the memory request. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240202144A1

公开(公告)日：2024-06-20

申请号：US18410554

申请日：2024-01-11

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Amit P. Apte ,  Eric Christopher Morton ,  Ganesh Balakrishnan ,  Ann M. Ling

IPC: G06F13/16 ,  G06F3/06

CPC classification number: G06F13/1673 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679 ,  G06F2213/0038

Abstract: A coherent memory fabric includes a plurality of coherent master controllers and a coherent slave controller. The plurality of coherent master controllers each include a response data buffer. The coherent slave controller is coupled to the plurality of coherent master controllers. The coherent slave controller, responsive to determining a selected coherent block read command is guaranteed to have only one data response, sends a target request globally ordered message to the selected coherent master controller and transmits responsive data. The selected coherent master controller, responsive to receiving the target request globally ordered message, blocks any coherent probes to an address associated with the selected coherent block read command until receipt of the responsive data is acknowledged by a requesting client.

公开(公告)号：US11874774B2

公开(公告)日：2024-01-16

申请号：US17031834

申请日：2020-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Ravindra N. Bhargava ,  Ganesh Balakrishnan ,  Joe Sargunaraj ,  Chintan S. Patel ,  Girish Balaiah Aswathaiya ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/08 ,  G06F12/0891 ,  G06F9/46 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/084

CPC classification number: G06F12/0891 ,  G06F9/467 ,  G06F12/084 ,  G06F12/0813 ,  G06F12/0833

Abstract: A method includes, in response to each write request of a plurality of write requests received at a memory-side cache device coupled with a memory device, writing payload data specified by the write request to the memory-side cache device, and when a first bandwidth availability condition is satisfied, performing a cache write-through by writing the payload data to the memory device, and recording an indication that the payload data written to the memory-side cache device matches the payload data written to the memory device.