Combined volatile nonvolatile array
    31.
    发明授权
    Combined volatile nonvolatile array 有权
    组合易失性非易失性阵列

    公开(公告)号:US07675775B2

    公开(公告)日:2010-03-09

    申请号:US11999684

    申请日:2007-12-05

    CPC classification number: G11C14/0018 G11C14/0063

    Abstract: A memory circuit includes volatile memory cells coupled to bit lines, and nonvolatile memory cells coupled to the volatile memory cells via the bit lines but not via complement bit lines.

    Abstract translation: 存储器电路包括耦合到位线的易失性存储器单元,以及经由位线而非经由补码位线耦合到易失性存储器单元的非易失性存储单元。

    COMBINATION MEMORY DEVICE AND SEMICONDUCTOR DEVICE
    32.
    发明申请
    COMBINATION MEMORY DEVICE AND SEMICONDUCTOR DEVICE 有权
    组合存储器件和半导体器件

    公开(公告)号:US20090323434A1

    公开(公告)日:2009-12-31

    申请号:US12485253

    申请日:2009-06-16

    Abstract: A combination memory device including a static random access memory (SRAM) and a read only memory (ROM) comprises first memory cells and second memory cells arranged in rows and columns, in which each of the first memory cells includes an SRAM cell and a ROM cell and is arranged adjacent to at least one of the second memory cells, and each of the second memory cells includes an SRAM cell and does not include a ROM cell.

    Abstract translation: 包括静态随机存取存储器(SRAM)和只读存储器(ROM)的组合存储器件包括排列成行和列的第一存储器单元和第二存储器单元,其中每个第一存储器单元包括SRAM单元和ROM 并且被布置为与第二存储器单元中的至少一个相邻,并且每个第二存储器单元包括SRAM单元,并且不包括ROM单元。

    Nonvolatile memory utilizing hot-carrier effect with data reversal function
    33.
    发明申请
    Nonvolatile memory utilizing hot-carrier effect with data reversal function 有权
    使用具有数据反转功能的热载波效应的非易失性存储器

    公开(公告)号:US20080186767A1

    公开(公告)日:2008-08-07

    申请号:US11701958

    申请日:2007-02-02

    CPC classification number: G11C14/00 G11C14/0063

    Abstract: A nonvolatile semiconductor memory device includes a control circuit, an inverting circuit, and memory units, each of the memory units including a latch having a first node and a second node, a plate line, a first MIS transistor having one of source/drain nodes coupled to the first node of the latch, another one of the source/drain nodes coupled to the plate line, and a gate node coupled to a word line, and a second MIS transistor having one of source/drain nodes coupled to the second node of the latch, another one of the source/drain nodes coupled to the plate line, and a gate node coupled to the word line, wherein the control circuit is configured to invert the data latched in the latch by reading the data from the latch, causing the inverting circuit to invert the read data, and writing the inverted data to the latch.

    Abstract translation: 非易失性半导体存储器件包括控制电路,反相电路和存储器单元,每个存储器单元包括具有第一节点和第二节点的锁存器,板线,具有源/漏节点之一的第一MIS晶体管 耦合到锁存器的第一节点,耦合到板线的源极/漏极节点中的另一个以及耦合到字线的栅极节点以及耦合到第二节点的源极/漏极节点之一的第二MIS晶体管 耦合到板线的源/漏节点中的另一个和耦合到字线的栅极节点,其中控制电路被配置为通过从锁存器读取数据来反转锁存在锁存器中的数据, 使反相电路反转读取的数据,并将反相数据写入锁存器。

    Three-dimensional non-volatile SRAM incorporating thin-film device layer

    公开(公告)号:US07280397B2

    公开(公告)日:2007-10-09

    申请号:US11179360

    申请日:2005-07-11

    CPC classification number: G11C14/00 G11C14/0063

    Abstract: A shadow RAM or “non-volatile SRAM” memory cell is implemented in a much smaller area by building the cell upward rather than outward. By stacking non-volatile storage devices above or below an SRAM cell, a smaller cell can be provided and result in a lower cost memory device. In certain embodiments, such a memory cell includes a pair of cross-coupled devices disposed on a first device layer and defining a pair of internal cross-coupled nodes, and a pair of non-volatile storage devices disposed on a second device layer above or below the pair of cross-coupled devices and coupled to the cross-coupled nodes.

    SRAM cell controlled by flash memory cell
    35.
    发明授权
    SRAM cell controlled by flash memory cell 失效
    由闪存单元控制的SRAM单元

    公开(公告)号:US07224603B1

    公开(公告)日:2007-05-29

    申请号:US11427456

    申请日:2006-06-29

    CPC classification number: G11C14/00 G11C11/412 G11C14/0063 H03K19/1776

    Abstract: First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupled to the second bit node. A second inverter has an input coupled to the second bit node and an output coupled to the first bit node through a first transistor switch. A transistor switch is coupled between the output of a non-volatile memory cell and the first bit node. A control circuit coupled to the gate of the transistor switch. Either the drive level of the non-volatile memory cell is selected to overpower the output of the second inverter or the second inverter is decoupled from the first bit node while the output of the non-volatile memory cell is coupled to the first bit node.

    Abstract translation: 第一和第二互补静态随机存取存储器单元位线通过由字线控制的第一和第二存取晶体管耦合到第一和第二位节点。 第一反相器具有耦合到第一位节点的输入和耦合到第二位节点的输出。 第二反相器具有耦合到第二位节点的输入和通过第一晶体管开关耦合到第一位节点的输出。 晶体管开关耦合在非易失性存储单元的输出和第一位节点之间。 耦合到晶体管开关的栅极的控制电路。 选择非易失性存储单元的驱动电平以使第二反相器的输出过压,或者第二反相器与第一位节点去耦,而非易失性存储单元的输出耦合到第一位节点。

    Three-dimensional non-volatile SRAM incorporating thin-film device layer
    36.
    发明申请
    Three-dimensional non-volatile SRAM incorporating thin-film device layer 有权
    三维非易失性SRAM结合薄膜器件层

    公开(公告)号:US20070008776A1

    公开(公告)日:2007-01-11

    申请号:US11179360

    申请日:2005-07-11

    Inventor: Roy Scheuerlein

    CPC classification number: G11C14/00 G11C14/0063

    Abstract: A shadow RAM or “non-volatile SRAM” memory cell is implemented in a much smaller area by building the cell upward rather than outward. By stacking non-volatile storage devices above or below an SRAM cell, a smaller cell can be provided and result in a lower cost memory device. In certain embodiments, such a memory cell includes a pair of cross-coupled devices disposed on a first device layer and defining a pair of internal cross-coupled nodes, and a pair of non-volatile storage devices disposed on a second device layer above or below the pair of cross-coupled devices and coupled to the cross-coupled nodes.

    Abstract translation: 阴影RAM或“非易失性SRAM”存储单元通过向上而不是向外建立单元来实现在更小的区域中。 通过在SRAM单元之上或之下堆叠非易失性存储设备,可以提供更小的单元并且导致较低成​​本的存储器件。 在某些实施例中,这种存储器单元包括一对交叉耦合器件,其布置在第一器件层上并限定一对内部交叉耦合节点,以及一对非易失性存储器件,其设置在第二器件层上方或 在交叉耦合器件对之下并耦合到交叉耦合节点。

    Nonvolatile semiconductor memory device
    37.
    发明申请
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号:US20060268622A1

    公开(公告)日:2006-11-30

    申请号:US11296431

    申请日:2005-12-08

    Applicant: Hee Kang Jin Ahn

    Inventor: Hee Kang Jin Ahn

    Abstract: A nonvolatile semiconductor memory device is provided for a high-powered system without the need for an additional system setting process to set the system initialization state after power-on to the previous state. The nonvolatile semiconductor memory device comprises a pull-up driving unit configured to include a plurality of nonvolatile cells for storing inputted data and to pull up a storage node, a pull-down driving unit configured to pull down the storage node, and a plurality of data registers including a data input/output unit configured to selectively input/output data between a bit line and the storage node depending on a voltage applied to a word line.

    Abstract translation: 为大功率系统提供非易失性半导体存储器件,而不需要额外的系统设置过程,以在上电之后将系统初始化状态设置为先前状态。 非易失性半导体存储器件包括:上拉驱动单元,被配置为包括用于存储输入数据和上拉存储节点的多个非易失性单元,被配置为将存储节点拉下来的下拉驱动单元,以及多个 数据寄存器,包括数据输入/输出单元,其配置为根据施加到字线的电压来选择性地在位线和存储节点之间输入/输出数据。

    Power loss compensation for programmable memory control system
    38.
    发明授权
    Power loss compensation for programmable memory control system 失效
    可编程存储器控制系统的功率损耗补偿

    公开(公告)号:US4523295A

    公开(公告)日:1985-06-11

    申请号:US415309

    申请日:1982-09-07

    Applicant: Thomas J. Zato

    Inventor: Thomas J. Zato

    CPC classification number: G11C14/0063 G06F1/30 G11B15/026 G11B31/006 G11C5/143

    Abstract: An arrangement for storing user programmed system timing information in a microprogrammable system in the event of a power outage. The system includes a static random access memory (RAM) for periodically storing microprocessor-generated timing information and an electrically erasable programmable ROM (EEPROM) which is coupled to the static RAM for the temporary storage of this information in the event of a power outage. Also provided in the system is a power down sensor responsive to an AC-coupled power supply for detecting power loss to the system. When the input voltage drops below a predetermined value, the contents of the static RAM are automatically transferred to the nonvolatile EEPROM. When system input power is restored, the stored contents of the nonvolatile EEPROM are automatically retransferred back to the static RAM for use by the microprocessor permitting the resumption of system operation as previously programmed on a time-shifted basis where the time shift equals the duration of the power outage. The system is particularly adapted for use with a user-programmed device, such as a television receiver or a video cassette recorder, in an environment where power outages of very short duration randomly occur. The present invention permits such a system to resume programmed system operation following resumption of power to the system without employing the combination of a battery, an oscillator, a CMOS RAM and appropriate recharging circuitry, as generally utilized in such systems.

    Abstract translation: 一种用于在断电情况下将用户编程的系统定时信息存储在微程序系统中的装置。 该系统包括用于周期性地存储微处理器产生的定时信息的静态随机存取存储器(RAM)和耦合到静态RAM的电可擦除可编程ROM(EEPROM),用于在断电的情况下临时存储该信息。 系统中还提供了响应于AC耦合电源的功率下降传感器,用于检测对系统的功率损耗。 当输入电压低于预定值时,静态RAM的内容将自动传输到非易失性EEPROM。 当系统输入电源恢复时,非易失性EEPROM的存储内容将自动重传回静态RAM,供微处理器使用,允许恢复系统操作,如先前在时移基础上编程的,其中时移等于 停电。 该系统特别适用于随机发生停电非常短的环境中的用户编程设备,例如电视接收机或录像机。 本发明允许这样的系统在恢复对系统的电力之后恢复编程系统操作,而不采用电池,振荡器,CMOS RAM和适当的充电电路的组合,如在这样的系统中一般使用的。

    Computing register with non-volatile-logic data storage

    公开(公告)号:US11990196B2

    公开(公告)日:2024-05-21

    申请号:US18179434

    申请日:2023-03-07

    CPC classification number: G11C29/36 G11C14/0063 G11C5/148 G11C2029/3602

    Abstract: A digital system includes a non-volatile calculating register having a set of latches configured to perform a calculation. A set of non-volatile storage cells is coupled to the set of latches. Access detection logic is coupled to the calculating register and is operable to initiate a calculation of a next value by the calculating register each time the calculating register is accessed by an accessing module. The access detection logic is operable to cause the next value to be stored in the set of non-volatile storage cells at the completion of the calculation as an atomic transaction. After a power loss or other restore event, the contents of the calculating register may be restored from the non-volatile storage cells.

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