-
公开(公告)号：US09858189B2
公开(公告)日：2018-01-02
申请号：US14748440
申请日：2015-06-24
Applicant: International Business Machines Corporation
Inventor： Michael Karl Gschwind , Valentina Salapura , Chung-Lung K. Shum
IPC: G06F12/08 , G06F12/0831 , G06F9/52 , G06F12/128 , G06F12/123 , G06F12/0817 , G06F9/46
CPC classification number: G06F12/0833 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/30145 , G06F9/3834 , G06F9/3859 , G06F9/3865 , G06F9/467 , G06F9/528 , G06F12/0817 , G06F12/0875 , G06F12/123 , G06F12/128 , G06F2212/1016 , G06F2212/452 , G06F2212/621 , G06F2212/69
Abstract: Embodiments of the invention relate to tracking processor transactional read and write sets, thereby eliminating speculative mis-predictions. Both non-speculative read set and write set indications are maintained for a transaction. The indications are stored in cache. In addition, load and write queues of addresses are maintained. The load queue of addresses relates to speculative members of a read set and the write queue of addresses relates to speculating member of a write set. For a received read request, a transaction resolution process takes place, and a resolution is performed if an address match in the write queue is detected. Similarly, for a receive write request the transaction interference additionally checks the load queue and the non-speculative read set for the pending address.
-
32.发明申请
公开(公告)号：US20170371701A1
公开(公告)日：2017-12-28
申请号：US15194226
申请日：2016-06-27
Applicant: KSHITIJ A. DOSHI , CHRISTOPHER J. HUGHES
Inventor： KSHITIJ A. DOSHI , CHRISTOPHER J. HUGHES
CPC classification number: G06F9/467 , G06F3/061 , G06F3/0637 , G06F3/0673
Abstract: Methods and apparatuses relating to hardware transactions are described. In one embodiment, a processor includes one or more cores to concurrently execute a plurality of transactions, and a hardware transactional circuit to detect an occurrence of a software selected precursor in any of the plurality of transactions and abort at least one of the plurality of transactions on the occurrence unless an interface to software indicates the occurrence is to not cause an abort, wherein the occurrence is not a memory access of shared data by the plurality of transactions.
-
公开(公告)号：US09817758B2
公开(公告)日：2017-11-14
申请号：US15408324
申请日：2017-01-17
Applicant: Intel Corporation
Inventor： Thomas Willhalm
IPC: G06F12/0811 , G06F12/0804 , G06F12/0875 , G06F12/0815
CPC classification number: G06F12/0804 , G06F9/467 , G06F12/0811 , G06F12/0815 , G06F12/0875 , G06F2212/202 , G06F2212/452 , G06F2212/60 , G06F2212/621
Abstract: A processor in described having an interface to non-volatile random access memory and logic circuitry. The logic circuitry is to identify cache lines modified by a transaction which views the non-volatile random access memory as the transaction's persistence storage. The logic circuitry is also to identify cache lines modified by a software process other than a transaction that also views said non-volatile random access memory as persistence storage.
-
公开(公告)号：US09798577B2
公开(公告)日：2017-10-24
申请号：US14841059
申请日：2015-08-31
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Guy L. Guthrie , Hung Q. Le , William J. Starke , Derek E. Williams
IPC: G06F12/08 , G06F9/46 , G06F12/0846 , G06F12/0855 , G06F12/0811 , G06F12/084 , G06F12/0817 , G06F12/0831 , G06F12/0862
CPC classification number: G06F9/467 , G06F12/0811 , G06F12/0828 , G06F12/0833 , G06F12/084 , G06F12/0846 , G06F12/0857 , G06F12/0862 , G06F2212/1016 , G06F2212/60 , G06F2212/6024 , G06F2212/621
Abstract: In at least some embodiments, a cache memory of a data processing system receives a transactional memory access request including a target address and a priority of the requesting memory transaction. In response, transactional memory logic detects a conflict for the target address with a transaction footprint of an existing memory transaction and accesses a priority of the existing memory transaction. In response to detecting the conflict, the transactional memory logic resolves the conflict by causing the cache memory to fail the requesting or existing memory transaction based at least in part on their relative priorities. Resolving the conflict includes at least causing the cache memory to fail the existing memory transaction when the requesting memory transaction has a higher priority than the existing memory transaction, the transactional memory access request is a transactional load request, and the target address is within a store footprint of the existing memory transaction.
-
公开(公告)号：US09792149B2
公开(公告)日：2017-10-17
申请号：US15249683
申请日：2016-08-29
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Michael K. Gschwind , Valentina Salapura
CPC classification number: G06F9/467 , G06F3/0619 , G06F3/0659 , G06F3/0665 , G06F3/0673 , G06F9/466 , G06F9/5038
Abstract: Controlling access to at least one memory location by a transaction is provided in a multi-processor transactional execution environment. Included is: tracking execution progress of a transaction, the execution progress being a metric of work performed for the transaction which includes at least one of instructions processed or cycles elapsed; based on encountering a conflict with another process for a memory location, comparing execution process of the transaction and execution progress of the other process; and deciding whether to continue the transaction based on the comparing. For instance, based on the execution progress of the transaction being greater than the execution progress of the other process, the transaction is continued, and based on the execution progress of the transaction being less that the execution progress of the other process, then the transaction is aborted.
-
公开(公告)号：US09785442B2
公开(公告)日：2017-10-10
申请号：US14582897
申请日：2014-12-24
Applicant: Elmoustapha Ould-Ahmed-Vall , Christopher J. Hughes , Robert Valentine , Milind B. Girkar
CPC classification number: G06F9/3016 , G06F9/30043 , G06F9/30087 , G06F9/30098 , G06F9/34 , G06F9/3455 , G06F9/3834 , G06F9/3842 , G06F9/3855 , G06F9/3859 , G06F9/3861 , G06F9/467
Abstract: Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for performing DSX comprises a hardware decoder to decode an instruction, the instruction to include an opcode and an operand to store a portion of a fallback address and an operand to store a stride value, execution hardware to execute the decoded instruction to initiate a data speculative execution (DSX) region by activating DSX tracking hardware to track speculative memory accesses and detect ordering violations in the DSX region, and storing the fallback address.
-
公开(公告)号：US20170286297A1
公开(公告)日：2017-10-05
申请号：US15507606
申请日：2015-04-03
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Douglas L. Voigt , Charles B. MORREY, III , Jishen ZHAO , Dhruva CHAKRABARTI , Joseph E. FOSTER
IPC: G06F12/0817 , G06F9/46 , G06F12/1009
CPC classification number: G06F12/0828 , G06F9/467 , G06F12/0238 , G06F12/08 , G06F12/1009 , G06F2212/1016 , G06F2212/1032 , G06F2212/222 , G06F2212/60 , G06F2212/621 , G06F2212/7201
Abstract: Example implementations may relate to a version controller allocating a copy page in persistent memory upon receiving, from an application executing on a processor, a copy command to version an image page for an atomic transaction. The version controller may receive application data addressed to a cache line of the image page, and may write the application data to a cache line of the copy page corresponding to the addressed cache line of the image page. If the version controller receives a replace-type transaction commit command, the version controller may generate a final page by either forward merging the image page into the copy page or backward merging the copy page into the image page, depending a merge direction policy.
-
公开(公告)号：US09767027B2
公开(公告)日：2017-09-19
申请号：US14328119
申请日：2014-07-10
Applicant: Microsoft Technology Licensing, LLC
Inventor： Jan Gray , David Callahn , Burton Jordan Smith , Gad Sheaffer , Ali-Reza Adl-Tabatabai
IPC: G06F12/0831 , G06F9/46 , G06F12/0811
CPC classification number: G06F12/0835 , G06F9/467 , G06F12/0811 , G06F12/0831 , G06F2209/521
Abstract: A system for optimizing cache coherence message traffic volume is disclosed. The system includes a plurality of caches in a multi-level memory hierarchy and a plurality of agents. Each agent is associated with a cache. The system includes one or more monitoring engines. Each agent in the plurality of agents is associated with a monitoring engine. The agents can execute a processor level software instruction causing a memory region to be private to the agent. Each of the agents is configured to execute a memory access for data on an associated cache and to send a request for data up the hierarchy on a cache miss. The monitoring engine is configured to intercept request for data from an agent and to prevent snooping for the cache line in peer caches when the cache line associated with a memory region represented as private to the agent.
-
公开(公告)号：US09766925B2
公开(公告)日：2017-09-19
申请号：US13789808
申请日：2013-03-08
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Dan F. Greiner , Christian Jacobi , Timothy J. Slegel
CPC classification number: G06F9/467 , G06F9/3004 , G06F9/30087 , G06F9/3834
Abstract: A transaction is initiated via a transaction begin instruction. During execution of the transaction, the transaction may abort. If the transaction aborts, a determination is made as to the type of transaction. Based on the transaction being a first type of transaction, resuming execution at the transaction begin instruction, and based on the transaction being a second type, resuming execution at an instruction following the transaction begin instruction. Regardless of transaction type, resuming execution includes restoring one or more registers specified in the transaction begin instruction and discarding transactional stores. For one type of transaction, the nonconstrained transaction, the resuming includes storing information in a transaction diagnostic block.
-
公开(公告)号：US09766829B2
公开(公告)日：2017-09-19
申请号：US14751919
申请日：2015-06-26
Applicant: International Business Machines Corporation
Inventor： Fadi Y. Busaba , Harold W. Cain, III , Dan F. Greiner , Michael K. Gschwind , Maged M. Michael , Eric M. Schwarz , Valentina Salapura , Timothy J. Slegel
IPC: G06F12/00 , G06F3/06 , G06F9/46 , G06F12/0815 , G06F12/0844
CPC classification number: G06F3/0622 , G06F3/0659 , G06F3/0673 , G06F9/466 , G06F9/467 , G06F9/52 , G06F12/0811 , G06F12/0815 , G06F12/084 , G06F12/0844 , G06F12/0862 , G06F12/1466 , G06F2212/6024 , G06F2212/621
Abstract: Embodiments relate to address probing for a transaction. An aspect includes determining, before starting execution of a transaction, a plurality of addresses that will be used by the transaction during execution. Another aspect includes probing each address of the plurality of addresses to determine whether any of the plurality of addresses has an address conflict. Yet another aspect includes, based on determining that none of the plurality of addresses has an address conflict, starting execution of the transaction.
