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公开(公告)号：US20180080983A1
公开(公告)日：2018-03-22
申请号：US15268463
申请日：2016-09-16
Applicant: QUALCOMM Incorporated
Inventor： Rama Rao Goruganthu , Gaurav Sunil Mattey , Martin Villafana
IPC: G01R31/311 , G01R31/28 , G01R1/07
CPC classification number: G01R31/311 , G01R1/071 , G01R31/2834
Abstract: A transparent coversheet intervenes between a lens and a thinned die in a visible light fault analysis tool so that the thinned die is robust to fractures. In addition, the transparent coversheet has a greater thermal mass than the thinned die and thus acts as a heat sink to prevent active circuitry in the thinned die from overheating during the visible light fault analysis.
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公开(公告)号：US20180075928A1
公开(公告)日：2018-03-15
申请号：US15648909
申请日：2017-07-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang Min LEE , Jae Hyung CHOI
CPC classification number: G11C29/52 , G01R31/2834 , G06F1/12 , G11C29/023 , G11C29/028 , G11C29/56012
Abstract: A memory system includes a memory device, and a memory controller. The controller adjusts a delay of a data strobe clock, performs at least one of a read test and a write test on the memory device, detect at least one data bit, which reduces at least one margin of a setup margin and a hold margin, from among a plurality of data bits, and adjusts a delay of the at least one data bit to allow the at least one margin to increase.
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公开(公告)号：US20180067162A1
公开(公告)日：2018-03-08
申请号：US15809389
申请日：2017-11-10
Applicant: International Business Machines Corporation
Inventor： Franco Motika , John D. Parker , Gerard M. Salem
IPC: G01R31/3177 , G01R31/317 , G01R31/28
CPC classification number: G01R31/3177 , G01R31/2834 , G01R31/31704 , G01R31/31724 , G01R31/318307 , G01R31/318371
Abstract: Embodiments include methods, computer systems and computer program products for generating functional test patterns for diagnostics, characterization and manufacture test. Aspects include: receiving from a system designer, via a design verification tool module, certain verification sequences configured to verify system functional design, executing the verification sequences received at a functional exerciser module against a device to generate various traces, capturing traces generated in emulation compatible format, processing traces captured via trace processor module, including parsing the traces captured, verifying data integrity of the traces captured, and summarizing statistics of the traces captured, generating, via an emulated pattern generator module, a predetermined number of emulated test patterns having tester independent format ‘streams’ of data compatible with a device test port based on output of the trace processor module, and processing, via a tester specific post-processor module, the emulated test patterns to generate functional test patterns using a tester specific post-processor module.
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公开(公告)号：US09864003B1
公开(公告)日：2018-01-09
申请号：US15619752
申请日：2017-06-12
Applicant: Advanced Testing Technologies, Inc. , Eli Levi
Inventor： Robert Spinner , Eli Levi , Jim McKenna , William Harold Leippe , William Biagiotti , Richard Engel
IPC: G01R31/28 , G01R1/04 , G01R31/3183
CPC classification number: G01R31/2834 , G01R1/0416 , G01R31/2851 , G01R31/3167 , G01R31/318342 , G01R31/31835 , G01R31/318357 , G01R31/31908
Abstract: A mixed signal testing system capable of testing differently configured units under test (UUT) includes a controller, a test station and an interface system that support multiple UUTs. The test station includes independent sets of channels configured to send signals to and receive signals from each UUT being tested and signal processing subsystems that direct stimulus signals to a respective set of channels and receive signals in response thereto. The signal processing subsystems enable simultaneous and independent directing of stimulus signals through the sets of channels to each UUT and reception of signals from each UUT in response to the stimulus signals. Received signals responsive to stimulus signals provided to a fully functional UUT (with and without induced faults) are used to assess presence or absence of faults in the UUT being tested which may be determined to include one or more faults or be fault-free, i.e., fully functional.
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公开(公告)号：US20180003764A1
公开(公告)日：2018-01-04
申请号：US15200997
申请日：2016-07-01
Applicant: Intel Corporation
Inventor： Sankaran M. Menon , Rehan M. Sheikh , Rolf H. Kuehnis , John Michael Peterson , Asifur Rahman , Abram M. Detofsky , Mohsen Fazlian
CPC classification number: G01R31/2834 , H04B1/40 , H04W4/80 , H04W24/06 , H04W88/06
Abstract: The disclosed systems, devices, and methods may provide for wireless testing of devices and, in particular, wireless testing of semiconductor devices comprising integrated circuits, memory, and logic circuitry that can be present on a wafer. The semiconductor devices can be tested for functional defects by applying one or more test patterns to the semiconductor devices. Further, for devices under test that do not have built-in wireless connectivity (for example, those that do not have a built-in Bluetooth low-energy engine), the disclosure describes systems and methods that the devices under test can use for external wireless connectivity (e.g., an external board having Bluetooth low-energy) on the low-bandwidth interface. In one example embodiment, for high-bandwidth scan testing, wireless connectivity modules (such as those implementing WiFi or WiGig) are described, which can be used to meet the bandwidth requirements of the one or more tests.
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公开(公告)号：US20170356956A1
公开(公告)日：2017-12-14
申请号：US15670592
申请日：2017-08-07
Applicant: Fluke Corporation
Inventor： John Neeley , Jordan Schlichting , Thomas McManus , Peter Bergstrom , Lindsey Berdan , Joseph V. Ferrante , Michael Devin Stuart
CPC classification number: G01R31/2834 , G06F11/2294
Abstract: A system for measuring a device under test (DUT) includes a computing device and a measurement device that measures an electrical or physical parameter of the DUT. The computing device receives and stores measurement data in a DUT record associated with the DUT. The computing device further obtains a first image of the DUT, displays the first image as a reference image with a first reference frame, receives a live image of the DUT from an image sensor, and displays the live image with a second reference frame that corresponds to the first reference frame. A cursor on the live image moves according to movement of the image sensor relative to the DUT. A second image of the DUT is obtained, wherein the second image is substantially aligned with the reference image based on an alignment of the cursor with the second reference frame. The second image is stored in the DUT record.
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公开(公告)号：US09841487B2
公开(公告)日：2017-12-12
申请号：US14928062
申请日：2015-10-30
Applicant: CHROMA ATE INC.
Inventor： Hou-Chun Chen , Shin-Wen Lin , Ching-Hua Chu , Po-Kai Cheng
CPC classification number: G01R35/005 , G01R31/2834 , G01R31/2882
Abstract: A calibration board and a timing calibration method thereof are provided. The calibration board for calibrating signal delays of test channels in an automatic test equipment is pluggably disposed in the automatic test equipment and includes calibration groups, a first common node, and a switching module. Each calibration group includes a second common node and conductive pads electrically connecting to the second common node. Each conductive pad selectively and electrically connects to one test channel. The switching module electrically connects to the first common node and each second common node. When a first delay calibration procedure is performed, the connection between the first common node and each second common node is disabled. When a second delay calibration procedure is performed, the connection between the first common node and each second common node is built.
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公开(公告)号：US09817064B1
公开(公告)日：2017-11-14
申请号：US15135184
申请日：2016-04-21
Applicant: Texas Instruments Incorporated
Inventor： Ramana Tadepalli
CPC classification number: G01R31/2834 , G01R31/31712 , G01R31/3172
Abstract: An I/O control circuit includes a plurality of IO cells including an input section for stimulating a plurality of (n) pins of a device under test (DUT) and an output section for processing data output by the pins. The input section of each cell includes a latched driver each including a driver input, a first driver output, a next state driver output, and a current source. The next state driver output and current source are for coupling to drive the pins, and the latched drivers are serially connected with the first driver output of an earlier IO cell connected to the driver input of a next IO cell. The output section of each cell includes an analog to digital converter (ADC) for coupling to the n pins, and a memory element coupled to an output of the ADC.
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公开(公告)号：US20170261552A1
公开(公告)日：2017-09-14
申请号：US15169842
申请日：2016-06-01
Applicant: International Business Machines Corporation
Inventor： Franco Motika , John D. Parker , Gerard M. Salem
IPC: G01R31/3177 , G01R31/317 , G01R31/28
CPC classification number: G01R31/3177 , G01R31/2834 , G01R31/31704 , G01R31/31724 , G01R31/318307 , G01R31/318371
Abstract: Embodiments include methods, computer systems and computer program products for generating functional test patterns for diagnostics, characterization and manufacture test. Aspects include: receiving from a system designer, via a design verification tool module, certain verification sequences configured to verify system functional design, executing the verification sequences received at a functional exerciser module against a device to generate various traces, capturing traces generated in emulation compatible format, processing traces captured via trace processor module, including parsing the traces captured, verifying data integrity of the traces captured, and summarizing statistics of the traces captured, generating, via an emulated pattern generator module, a predetermined number of emulated test patterns having tester independent format ‘streams’ of data compatible with a device test port based on output of the trace processor module, and processing, via a tester specific post-processor module, the emulated test patterns to generate functional test patterns using a tester specific post-processor module.
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公开(公告)号：US20170261545A1
公开(公告)日：2017-09-14
申请号：US15510371
申请日：2015-09-09
Applicant: ENICS AG
Inventor： Kristian FEDERLEY , Jukka MATTILA
IPC: G01R31/28
CPC classification number: G01R31/2834 , G01R31/2839 , G01R31/31703
Abstract: A method of testing an electronic unit by comparing resulting signal shapes from the unit to be tested and a known functioning unit. The method includes powering off the units for testing and feeding one or more predefined signal shapes of two or more different frequencies as input signals to the known functioning unit and to the unit to be tested at corresponding test points. The method further includes measuring the resulting signal shapes from both units at corresponding measurement points and comparing at least one resulting signal shape from the known functioning unit with the corresponding resulting signal shape from the unit to be tested. The method also includes detecting a fault in the unit to be tested on the basis of an existing signal shape distortion in time axis of the resulting signal shape received from the unit to be tested.
