公开(公告)号：US11204556B2

公开(公告)日：2021-12-21

申请号：US16995759

申请日：2020-08-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chih Huang ,  Chi Yang ,  Che-Chang Hsu ,  Li-Jui Chen ,  Po-Chung Cheng

IPC: G03F7/20

Abstract: A method of controlling a feedback system with a data matching module of an extreme ultraviolet (EUV) radiation source is disclosed. The method includes obtaining a slit integrated energy (SLIE) sensor data and diffractive optical elements (DOE) data. The method performs a data match, by the data matching module, of a time difference of the SLIE sensor data and the DOE data to identify a mismatched set of the SLIE sensor data and the DOE data. The method also determines whether the time difference of the SLIE sensor data and the DOE data of the mismatched set is within an acceptable range. Based on the determination, the method automatically validates a configurable data of the mismatched set such that the SLIE sensor data of the mismatched set is valid for a reflectivity calculation.

公开(公告)号：US20210091065A1

公开(公告)日：2021-03-25

申请号：US17113204

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Cheng Tseng ,  Yu-Chih Huang ,  Chih-Hsuan Tai ,  Ting-Ting Kuo ,  Chi-Hui Lai ,  Ban-Li Wu ,  Chiahung Liu ,  Hao-Yi Tsai

IPC: H01L27/01 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02 ,  H01L21/768 ,  H01L21/70 ,  H01L23/522

Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.

公开(公告)号：US20200327214A1

公开(公告)日：2020-10-15

申请号：US16914609

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chih Huang ,  Chih-Hsuan Tai ,  Yu-Jen Cheng ,  Chih-Hua Chen ,  Yu-Feng Chen ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: G06F21/32 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/58 ,  G06K9/00 ,  H01L21/48 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00

Abstract: A device package includes a sensor die, one or more additional dies adjacent the sensor die, and a molding compound encircling the sensor die and the one or more additional dies. The device package further includes redistribution layers over the sensor die, the one or more additional dies, and the molding compound. The redistribution layers include first conductive features in a first dielectric layer. The first conductive features electrically connect the sensor die to the one or more additional dies. The redistribution layers further include an array of electrodes in a second dielectric layer over the first dielectric layer and electrically connected to the sensor die.

公开(公告)号：US20200294912A1

公开(公告)日：2020-09-17

申请号：US16354173

申请日：2019-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Tsung-Hsien Chiang ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Po-Chun Lin

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/48 ,  H01L23/528 ,  H01L21/56 ,  H01L21/768

Abstract: A package structure includes a die, a TIV, a first encapsulant, a RDL structure, a thermal dissipation structure and a second encapsulant. The die has a first surface and a second surface opposite to each other. The TIV is laterally aside the die. The first encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The RDL structure is disposed on the first surface of the die and on the first encapsulant, electrically connected to the die and the TIV. The thermal dissipation structure is disposed over the second surface of die and electrically connected to the die through the TIV and the RDL structure. The second encapsulant encapsulates sidewalls of the thermal dissipation structure.

公开(公告)号：US10672729B2

公开(公告)日：2020-06-02

申请号：US15726260

申请日：2017-10-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hsuan Tai ,  Ting-Ting Kuo ,  Yu-Chih Huang ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Chih-Hua Chen ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Hao-Yi Tsai ,  Chung-Shi Liu

IPC: H01L21/683 ,  H01L23/00 ,  H01L23/31

Abstract: A method of forming a package structure includes disposing a semiconductor device over a first dielectric layer, wherein a first redistribution line is in the first dielectric layer, forming a molding compound over the first dielectric layer and in contact with a sidewall of the semiconductor device, forming a second dielectric layer over the molding compound and the semiconductor device, forming a first opening in the second dielectric layer, the molding compound, and the first dielectric layer to expose the first redistribution line, and forming a first conductor in the first opening, wherein the first conductor is electrically connected to the first redistribution line.

公开(公告)号：US20200058626A1

公开(公告)日：2020-02-20

申请号：US16103921

申请日：2018-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ting-Ting Kuo ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Chi-Hui Lai

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.

公开(公告)号：US10510631B2

公开(公告)日：2019-12-17

申请号：US15706783

申请日：2017-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsuan Tai ,  Chih-Hua Chen ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ting-Ting Kuo

IPC: H01L21/56 ,  H01L23/532 ,  H01L23/522 ,  H01L21/78 ,  H01L25/065 ,  H01L23/31 ,  H01L21/66 ,  H01L23/00

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, a redistribution layer (RDL) structure, a through integrated fan-out via (TIV) and a first connector. The RDL structure is connected to the die and includes a plurality of RDLs. The TIV is aside the die and penetrates through the RDL structure. The first connector is in electrical contact with the TIV and electrically connected to the die. The TIV is in electrical contact with the RDLs of the RDL structure.

公开(公告)号：US20190088564A1

公开(公告)日：2019-03-21

申请号：US15706783

申请日：2017-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsuan Tai ,  Chih-Hua Chen ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ting-Ting Kuo

IPC: H01L23/31 ,  H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/532 ,  H01L23/522

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, a redistribution layer (RDL) structure, a through integrated fan-out via (TIV) and a first connector. The RDL structure is connected to the die and includes a plurality of RDLs. The TIV is aside the die and penetrates through the RDL structure. The first connector is in electrical contact with the TIV and electrically connected to the die. The TIV is in electrical contact with the RDLs of the RDL structure.

公开(公告)号：US10157808B2

公开(公告)日：2018-12-18

申请号：US15679027

申请日：2017-08-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hsuan Tai ,  Ting-Ting Kuo ,  Yu-Chih Huang ,  Chih-Hua Chen ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H04L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L23/522 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

Abstract: A package structure includes a semiconductor device, a first molding compound, a through-via, a first dielectric layer, a first redistribution line, and a second molding compound. The first molding compound is in contact with a sidewall of the semiconductor device. The through-via is in the first molding compound and is electrically connected to the semiconductor device. The first dielectric layer is over the semiconductor device. The first redistribution line is in the first dielectric layer and is electrically connected to the semiconductor device and the through-via. The second molding compound is in contact with a sidewall of the first dielectric layer.

公开(公告)号：US09691708B1

公开(公告)日：2017-06-27

申请号：US15214475

申请日：2016-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chih Huang ,  Chih-Hua Chen ,  Chih-Wei Lin ,  Hao-Yi Tsai ,  Yu-Feng Chen ,  Yu-Jen Cheng ,  Chih-Hsuan Tai

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/58 ,  H01L23/00 ,  G06K9/00

CPC classification number: H01L23/5389 ,  G06K9/0002 ,  G06K9/00053 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/83005

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution layer, a second redistribution layer, and a plurality of through interlayer vias. The molded semiconductor device includes a die. The first redistribution layer is disposed on a first side of the molded semiconductor device. The second redistribution layer is disposed on a second side of the molded semiconductor device opposite to the first side, wherein the second redistribution layer includes a patterned metal layer having an interconnection circuit portion electrically connected to the die and a metal ring surrounding and insulated from the interconnection circuit portion. The through interlayer vias are located right under the metal ring and extending through the molded semiconductor device to be electrically connect the first redistribution layer and the second redistribution layer.