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    SEMICONDUCTOR DEVICE
    31.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230380176A1

    公开(公告)日：2023-11-23

    申请号：US18102349

    申请日：2023-01-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Daewon HA ,  Kyunghwan LEE ,  Youngnam Hwang

    IPC: H10B51/30 ,  H10B51/40

    CPC classification number: H10B51/30 ,  H10B51/40

    Abstract: A semiconductor device includes a cell region including a plurality of memory cells, and a peripheral circuit region controlling the plurality of memory cells. Each of the plurality of memory cells includes a first active region and a second active region adjacent to each other, a first channel layer and a second channel layer extending in the first direction, connected to the first active region and the second active region, and separated from each other in the third direction, a first ferroelectric layer and a first gate electrode layer sequentially provided on the first channel layer, and a second ferroelectric layer and a second gate electrode layer sequentially provided on the second channel layer. The first gate electrode layer and the second gate electrode layer are separated from each other in the third direction.

    THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE INCLUDING HORIZONTAL CHANNEL REGION
    32.
    发明公开
    THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE INCLUDING HORIZONTAL CHANNEL REGION 审中-公开

    公开(公告)号：US20230292522A1

    公开(公告)日：2023-09-14

    申请号：US18055974

    申请日：2022-11-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Daewon HA ,  Kyunghwan LEE ,  Hyunmog PARK

    IPC: H01L21/02

    CPC classification number: H10B51/20 ,  H10B51/10 ,  H10B51/40

    Abstract: A three-dimensional non-volatile memory device includes a memory cell array including a plurality of memory cells repeatedly arranged in a first lateral direction, a second lateral direction, and a vertical direction on a substrate. The first lateral direction and the second lateral direction are parallel to a main surface of the substrate and perpendicular to each other, and the vertical direction is perpendicular to the main surface of the substrate. The memory cell array includes a plurality of horizontal channel regions and a vertical word line. The plurality of horizontal channel regions extend in the first lateral direction on the substrate. The plurality of horizontal channel regions overlap each other and are apart from each other in the vertical direction. The vertical word line passes through the plurality of horizontal channel regions in the vertical direction.

    MEMORY DEVICE
    33.
    发明公开
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20230180453A1

    公开(公告)日：2023-06-08

    申请号：US18054986

    申请日：2022-11-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Kyunghwan LEE ,  Minjun LEE ,  Daewon HA

    IPC: H01L27/108

    CPC classification number: H01L27/10802

    Abstract: A memory device is provided. The memory device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a first source/drain at one end of the fin structure, and a second source/drain at the other end of the fin structure, wherein the gate structure includes a trap layer, a blocking layer, and a gate electrode layer sequentially stacked on the fin structure, the first source/drain is doped with or has incorporated therein dopants of a first conductivity-type, and the second source/drain is doped with or has incorporated therein dopants of a second conductivity-type dopants that are different from the dopants of the first conductivity-type.

    SEMICONDUCTOR MEMORY DEVICE OF 2T-1C STRUCTURE AND METHOD OF FABRICATING THE SAME
    34.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE OF 2T-1C STRUCTURE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20230101700A1

    公开(公告)日：2023-03-30

    申请号：US17881747

    申请日：2022-08-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Hyuncheol KIM ,  Jongman PARK ,  Dongsoo WOO ,  Minjun LEE

    IPC: H01L27/108

    Abstract: A semiconductor memory device may include first and second bit lines spaced apart from each other, an interlayer insulating layer covering the first and second bit lines and including a groove extending to cross both of the first and second bit lines, a first channel pattern connected to the first bit line and in contact with an inner side surface of the groove and covering a top surface of the interlayer insulating layer, a second channel pattern connected to the second bit line and in contact with an opposite inner side surface of the groove and covering the top surface of the interlayer insulating layer, a word line in the groove, first and second electrodes on the interlayer insulating layer and in contact with the first and second channel patterns, respectively, and a dielectric layer between the first and second electrodes.

    ELECTRONIC APPARATUS TRAINING INDIVIDUAL MODEL OF USER AND METHOD OF OPERATING THE SAME
    35.
    发明申请
    ELECTRONIC APPARATUS TRAINING INDIVIDUAL MODEL OF USER AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20220004874A1

    公开(公告)日：2022-01-06

    申请号：US17480859

    申请日：2021-09-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： James Russell GERACI ,  Kyunghwan LEE

    IPC: G06N3/08 ,  G06K9/62 ,  G06N3/10

    Abstract: A method and an electronic apparatus for training a personal model of a user are provided. The method includes obtaining first information including personal data of the user represented as a first constituent element of the personal model; obtaining second information including group data of a plurality of users in a group to which the user belongs, represented as a second constituent element of the personal model; determining a first weight value and a second weight value to be respectively applied to the first information and the second information based on reliability of the first information; and training the personal model based on the first information and the second information to which the first weight value and the second weight value are respectively applied.

    SEMICONDUCTOR MEMORY DEVICE
    36.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210225842A1

    公开(公告)日：2021-07-22

    申请号：US16999378

    申请日：2020-08-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Satoru YAMADA ,  Sungwon YOO ,  Kyunghwan LEE ,  Jaeho HONG

    IPC: H01L27/102 ,  H01L29/24

    Abstract: A semiconductor memory device may include a first electrode and a second electrode, which are spaced apart from each other in a first direction, and a first semiconductor pattern, which is in contact with both of the first and second electrodes. The first semiconductor pattern may include first to fourth sub-semiconductor patterns, which are sequentially disposed in the first direction. The first and fourth sub-semiconductor patterns may be in contact with the first and second electrodes, respectively. The first and third sub-semiconductor patterns may be of a first conductivity type, and the second and fourth sub-semiconductor patterns may be of a second conductivity type different from the first conductivity type. Each of the first to fourth sub-semiconductor patterns may include a transition metal and a chalcogen element.

    ELECTRONIC DEVICE COMPRISING PLURALITY OF BATTERIES, AND OPERATING METHOD THEREOF
    39.
    发明申请
    ELECTRONIC DEVICE COMPRISING PLURALITY OF BATTERIES, AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20250132588A1

    公开(公告)日：2025-04-24

    申请号：US18990356

    申请日：2024-12-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyunghwan LEE

    IPC: H02J7/00 ,  H01M50/519

    Abstract: An electronic device includes: first and second batteries; a charging circuit to supply power to the first battery through a first path and supply power to the second battery through a second path; and a processor to control the charging circuit to generate a current corresponding to a sum of a first threshold current of the first battery and a second threshold current of the second battery based on power received from a power transmitter, control the charging circuit to supply a first current to the first battery through the first path and supply a second current to the second battery through the second path based on the current, identify the second current supplied to the second battery, and control the charging circuit such that the magnitude of the second current supplied to the second battery is reduced based on the second current exceeding the second threshold current.

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