公开(公告)号：US20170092592A1

公开(公告)日：2017-03-30

申请号：US15083827

申请日：2016-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Hyeonjin SHIN ,  Changhyun KIM ,  Changseok LEE ,  Seongjun PARK ,  Hyunjae SONG

IPC: H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53276 ,  H01L23/485 ,  H01L23/5283

Abstract: A hybrid interconnect structure includes a graphene layer between a non-metallic material layer and a metal layer, and a first interfacial bonding layer between the non-metallic material layer and the graphene layer, or the metal layer and the graphene layer. The graphene layer connects the non-metallic material layer and the metal layer, and the first bonding layer includes a metallic material.

公开(公告)号：US20160351491A1

公开(公告)日：2016-12-01

申请号：US15052290

申请日：2016-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseok LEE ,  Keunwook SHIN ,  Hyeonjin SHIN ,  Seongjun PARK ,  Hyunjae SONG ,  Hyangsook LEE ,  Yeonchoo CHO

IPC: H01L23/528 ,  H01L27/06 ,  H01L23/532

CPC classification number: H01L27/0629 ,  H01L23/53271 ,  H01L27/101 ,  H01L27/228

Abstract: A wiring structure may include at least two conductive material layers and a two-dimensional layered material layer in an interface between the at least two conductive material layers. The two-dimensional layered material layer may include a grain expander layer which causes grain size of a conductive material layer which is on the two-dimensional layered material layer to be increased. Increased grain size may result in resistance of the second conductive material layer to be reduced. As a result, the total resistance of the wiring structure may be reduced. The two-dimensional layered material layer may contribute to reducing a total thickness of the wiring structure. Thus, a low-resistance and high-performance wiring structure without an increase in a thickness thereof may be implemented.

Abstract translation: 布线结构可以包括在至少两个导电材料层之间的界面中的至少两个导电材料层和二维层状材料层。 二维层状材料层可以包括使二维层状材料层上的导电性材料层的粒径增大的晶粒扩展层。 增加的晶粒尺寸可能导致第二导电材料层的电阻降低。 结果，可以减小布线结构的总电阻。 二维层状材料层可有助于减小布线结构的总厚度。 因此，可以实现不增加其厚度的低电阻和高性能布线结构。

公开(公告)号：US20150093648A1

公开(公告)日：2015-04-02

申请号：US14499624

申请日：2014-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhyuk SON ,  Hyunjae SONG ,  Inyong SONG ,  Jaeman CHOI ,  Seungsik HWANG ,  Junhwan KU ,  Jonghwan PARK ,  Yeonji CHUNG

IPC: H01B1/04 ,  H01B13/00 ,  H01M4/04 ,  H01M4/1393 ,  H01M4/36 ,  H01M4/62

CPC classification number: H01B1/04 ,  H01B13/0016 ,  H01B13/0026 ,  H01M4/0428 ,  H01M4/134 ,  H01M4/1393 ,  H01M4/366 ,  H01M4/386 ,  H01M4/48 ,  H01M4/587 ,  H01M4/625 ,  Y10T428/292

Abstract: A composite including: silicon (Si); a silicon oxide of the formula SiOx, wherein 0

Abstract translation: 包括：硅（Si）; 式SiO x的氧化硅，其中0