Display device with clock signal modification during vertical blanking period

    公开(公告)号:US10395616B2

    公开(公告)日:2019-08-27

    申请号:US15443566

    申请日:2017-02-27

    Abstract: A display apparatus includes a display panel comprising a pixel which is connected to a gate line and a data line, a gate driver configured to generate a gate signal having a gate-on voltage and a gate-off voltage and to provide the gate line with the gate signal, and a gate controller configured to generate a clock signal having a duty ratio and to provide the gate driver with the clock signal, where a mean amplitude of the clock signal in a vertical blanking period of a frame cycle is smaller than the mean amplitude of the clock signal in an active period of the frame cycle.

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