公开(公告)号：US20110058642A1

公开(公告)日：2011-03-10

申请号：US12649341

申请日：2009-12-30

申请人： Tsung-Ting Tsai ,  Yung-Chih Chen

发明人： Tsung-Ting Tsai ,  Yung-Chih Chen

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3677 ,  G09G2310/0286

摘要： A shift register circuit includes a plurality of shift register stages for providing plural gate signals to plural gate lines. Each shift register stage includes an input unit, a first pull-up unit, a second pull-up unit, a pull-down unit and an auxiliary pull-down unit. The input unit inputs a first gate signal generated by a preceding shift register stage to become a driving control voltage. The first pull-up unit pulls up a second gate signal according to the driving control voltage and a first clock signal. The second pull-up unit pulls up a third gate signal according to the driving control voltage and a second clock signal. The auxiliary pull-down unit is employed to pull down the driving control voltage according to a fourth gate signal generated by a subsequent shift register stage. The pull-down unit pulls down the first and second gate signals according to the driving control voltage.

公开(公告)号：US20110050550A1

公开(公告)日：2011-03-03

申请号：US12584221

申请日：2009-09-01

申请人： Tsung-Ting Tsai ,  Lee-Hsun Chang

发明人： Tsung-Ting Tsai ,  Lee-Hsun Chang

IPC分类号： G09G3/30

CPC分类号： G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0439 ,  G09G2300/0465 ,  G09G2300/0842 ,  G09G2300/0852 ,  G09G2320/0223 ,  G09G2320/0233 ,  G09G2330/02 ,  H01L27/326

摘要： A display panel has a plurality of OLED pixels arranged in rows and columns. The pixel driving circuit has two or more current paths through a plurality of switching elements for providing the necessary current to the OLEDs in a pixel. The control end of each switching element is connected to the control end of the other switching elements, but each switching element has a separate power source which can be separately adjustable. In some embodiments, in a pixel or sub-pixel, one switching element is located at one end and one switching element is located at the other end of a pixel length, and each pixel is adjacent to a first power source line and a second power source line along the pixel length for separately providing the electrical power to two switching elements.

摘要翻译： 显示面板具有以行和列排列的多个OLED像素。 像素驱动电路具有穿过多个开关元件的两个或多个电流路径，用于向像素中的OLED提供必要的电流。 每个开关元件的控制端连接到其他开关元件的控制端，但是每个开关元件具有可单独调节的单独的电源。 在一些实施例中，在像素或子像素中，一个开关元件位于一端，一个开关元件位于像素长度的另一端，并且每个像素与第一电源线和第二电源相邻 源极线沿像素长度分开提供电力到两个开关元件。

公开(公告)号：US20100150302A1

公开(公告)日：2010-06-17

申请号：US12334874

申请日：2008-12-15

申请人： Tsung-Ting TSAI ,  Ming-Sheng LAI ,  Min-Feng CHIANG ,  Po-Yuan LIU

发明人： Tsung-Ting TSAI ,  Ming-Sheng LAI ,  Min-Feng CHIANG ,  Po-Yuan LIU

IPC分类号： G11C19/00

CPC分类号： G11C19/28

摘要： A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn−1 and the stage Sn+1.

摘要翻译： 移位寄存器包括多个级，{Sn}，n = 1,2。 。 。 ，N，N为正整数。 在一个实施例中，每级Sn包括一个上拉电路，该上拉电路具有用于接收第一时钟信号CK1和第二时钟信号XCK1中的一个的输入端，用于响应地输出输出信号的输出端和输入节点 Qn是电耦合到输入节点Qn并被配置为使得当接收到第一输入信号时，上拉控制电路响应地产生提供给输入节点Qn的信号，以接通上拉电路， 电耦合到输入节点Qn并被配置为向输入节点Qn和上拉电路的输出之一提供第一电压的下拉电路，以及被配置为接收一个电压的下拉控制电路 第三时钟信号CK2和第四时钟信号XCK2，并且响应地产生第一电压以接通级Sn的下拉电路和级Sn-1之一的下拉电路和 阶段Sn + 1。

公开(公告)号：US20100109738A1

公开(公告)日：2010-05-06

申请号：US12291006

申请日：2008-11-04

申请人： Chih Yuan Chien ,  Tsung-Ting Tsai

发明人： Chih Yuan Chien ,  Tsung-Ting Tsai

IPC分类号： H03K3/02

CPC分类号： G09G3/3677 ,  G09G3/3607 ,  G09G3/3659 ,  G09G2300/0426 ,  G09G2310/0205 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2320/0242 ,  G11C19/28

摘要： A gate driver for use in a liquid crystal display has a plurality of shift registers connected in series. Each of the shift registers is used to provide a gate-line pulse to a row of pixels in the liquid crystal display. The gate-line pulse has a front pulse and a rear pulse and the shift register has a front-pulse generating part and a rear-pulse generating part for generating to corresponding pulse. Each of the pulse generating parts has a first pull-up circuit to generate a voltage level to keep a switching element in a second pull-up circuit conducting so as to generate a front or rear pulse, in response to a corresponding clock signal, and two pull-down circuits, in response to the voltage level, to allow the front or rear pulse to be generated only at a pull-down period.

摘要翻译： 用于液晶显示器的栅极驱动器具有串联连接的多个移位寄存器。 每个移位寄存器用于向液晶显示器中的一行像素提供栅极线脉冲。 栅极脉冲具有前脉冲和后脉冲，并且移位寄存器具有用于产生相应脉冲的前脉冲产生部分和后脉冲产生部分。 每个脉冲发生部分具有第一上拉电路，以产生电压电平，以响应于对应的时钟信号，将开关元件保持在第二上拉电路中，以产生前或后脉冲;以及 两个下拉电路响应于电压电平，以允许仅在下拉周期产生前脉冲或后脉冲。

公开(公告)号：US11154330B1

公开(公告)日：2021-10-26

申请号：US17197184

申请日：2021-03-10

申请人： Yun-Da Li ,  Ching-Lung Tai ,  Po-Liang Lai ,  Tsung-Ting Tsai ,  Ming-Kai Hsieh ,  Mu-Yi Liu

发明人： Yun-Da Li ,  Ching-Lung Tai ,  Po-Liang Lai ,  Tsung-Ting Tsai ,  Ming-Kai Hsieh ,  Mu-Yi Liu

IPC分类号： A61B17/70

摘要： A dual-trajectory pedicle screw system includes an internally threaded sleeve and including first part and cylindrical second part, the first part being recessed to form a space, and the second part including projections on top; a main screw including a universal head and a first conic member, the universal head including first and second threaded holes, the first threaded hole being inclined at a first angle, the second threaded hole being inclined at a different second angle, bottom of the universal head being a convex and rotatably disposed in the space; and an auxiliary screw including external threads threadedly secured to the first or second threaded hole so that the auxiliary screw is secured to the main screw at the first or second angle with respect to the main screw, a second conic member extending downward from the external threads, and a fitting member on top of the external threads.

公开(公告)号：US08587574B2

公开(公告)日：2013-11-19

申请号：US12764980

申请日：2010-04-22

申请人： Tsung-Ting Tsai

发明人： Tsung-Ting Tsai

IPC分类号： G06F3/038 ,  G09G5/00

CPC分类号： H01L27/3279 ,  G09G2300/0426 ,  G09G2320/0223 ,  H01L27/3211

摘要： A pixel structure of an electroluminescent display panel includes a plurality of sub-pixel columns, first power lines, and second power lines. Each of the first power lines and each of the second power lines are disposed between two adjacent sub-pixel columns. Each first power line is electrically connected to a portion of sub-pixels of a sub-pixel column disposed on one side of the first power line, and a portion of sub-pixels of the other sub-pixel column disposed on the other side of the first power line. Each second power line is electrically connected to a portion of sub-pixels of a sub-pixel column disposed on one side of the second power line, and a portion of sub-pixels of the other sub-pixel column disposed on the other side of the second power line.

摘要翻译： 电致发光显示面板的像素结构包括多个子像素列，第一电力线和第二电力线。 第一电力线和第二电力线中的每一个被布置在两个相邻的子像素列之间。 每个第一电力线电连接到设置在第一电力线的一侧上的子像素列的子像素的一部分，并且另一个子像素列的子像素的一部分设置在另一个子像素列的另一侧 第一条电力线。 每个第二电源线电连接到设置在第二电力线的一侧上的子像素列的子像素的一部分，另一个子像素列的子像素的一部分设置在第二电源线的另一侧 第二条电力线。

公开(公告)号：US08581890B2

公开(公告)日：2013-11-12

申请号：US12684905

申请日：2010-01-09

申请人： Yung-Chih Chen ,  Tsung-Ting Tsai ,  Kuo-Chang Su ,  Chun-Hsin Liu

发明人： Yung-Chih Chen ,  Tsung-Ting Tsai ,  Kuo-Chang Su ,  Chun-Hsin Liu

IPC分类号： G06F3/038

CPC分类号： G09G3/3677 ,  G09G2310/0251 ,  G09G2320/0219

摘要： In a liquid crystal display, a flat display and a gate driving method thereof, the flat display comprises first and second pixel rows, first to third gate lines and a gate driving circuit. The first gate line is for determining whether to turn on a portion of pixels in the first pixel row, the second gate line is for determining whether to turn on another portion of pixels in the first pixel row, and the third gate line is for determining whether to turn on a portion of the pixels in the second pixel row. The gate driving circuit is for providing first to third gate driving pulses to the first to third gate lines. The first and second gate driving pulses do not overlap with each other, and the third gate driving pulse partially overlaps with one of the first and second gate driving pulses.

摘要翻译： 在液晶显示器，平板显示器及其栅极驱动方法中，平面显示器包括第一和第二像素行，第一至第三栅极线和栅极驱动电路。 第一栅极线用于确定是否接通第一像素行中的一部分像素，第二栅极线用于确定是否接通第一像素行中的另一部分像素，并且第三栅极线用于确定 是否打开第二像素行中的像素的一部分。 栅极驱动电路用于向第一至第三栅极线提供第一至第三栅极驱动脉冲。 第一和第二栅极驱动脉冲彼此不重叠，并且第三栅极驱动脉冲与第一和第二栅极驱动脉冲中的一个部分重叠。

公开(公告)号：US08421781B2

公开(公告)日：2013-04-16

申请号：US12636801

申请日：2009-12-14

申请人： Yung-Chih Chen ,  Chun-Hsin Liu ,  Tsung-Ting Tsai ,  Kuo-Chang Su

发明人： Yung-Chih Chen ,  Chun-Hsin Liu ,  Tsung-Ting Tsai ,  Kuo-Chang Su

IPC分类号： G06F3/038

CPC分类号： G09G3/3677 ,  G09G2310/0286 ,  G09G2320/0209

摘要： A shift register has a plurality of shift register units coupled in series. Each shift register includes a pull-up circuit, an input circuit, a pull-down circuit, a compensation circuit, an input end, an output end and a node. Each shift register unit receives an input voltage at the input end and provides an output voltage at the output end. The input circuit transmits the input voltage to the node based on a first clock signal. The pull-up circuit provides the output voltage based on a second clock signal and the voltage level of the node. The pull-down circuit selectively connects the node with the output end according to a third clock signal. The compensation circuit is coupled to the input circuit, the pull-down circuit and the node for maintaining the voltage level of the node based on the second and third clock signals.

摘要翻译： 移位寄存器具有串联耦合的多个移位寄存器单元。 每个移位寄存器包括上拉电路，输入电路，下拉电路，补偿电路，输入端，输出端和节点。 每个移位寄存器单元在输入端接收输入电压，并在输出端提供输出电压。 输入电路基于第一时钟信号将输入电压发送到节点。 上拉电路基于第二时钟信号和节点的电压电平提供输出电压。 下拉电路根据第三时钟信号选择性地将节点与输出端连接。 补偿电路耦合到输入电路，下拉电路和节点，用于基于第二和第三时钟信号来维持节点的电压电平。

公开(公告)号：US08340240B2

公开(公告)日：2012-12-25

申请号：US13492916

申请日：2012-06-10

申请人： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Chun-Hsin Liu

发明人： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Chun-Hsin Liu

IPC分类号： G11C19/00

CPC分类号： G11C19/00 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G09G2320/0219 ,  G11C19/28

摘要： A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.

摘要翻译： 移位寄存器包括串联耦合的多个移位寄存器单元。 接收输入端的输入电压和输出端的输出电压的每个移位寄存器单元包括节点，上拉驱动电路，上拉电路和第一至第三下拉电路。 上拉驱动电路可以将输入电压传输到节点，并且上拉电路可以基于高频时钟信号和输入信号提供输出电压。 第一下拉电路可以基于第一低频时钟信号在节点处或在输出端提供偏置电压。 第二下拉电路可以基于第二低频时钟信号在节点处或在输出端提供偏置电压。 第三下拉电路可以基于反馈电压在节点处或输出端提供偏置电压。

公开(公告)号：US08229058B2

公开(公告)日：2012-07-24

申请号：US12607042

申请日：2009-10-27

申请人： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Chun-Hsin Liu

发明人： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Chun-Hsin Liu

IPC分类号： G11C19/00

CPC分类号： G11C19/00 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G09G2320/0219 ,  G11C19/28

摘要： A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.