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公开(公告)号：US10594327B2
公开(公告)日：2020-03-17
申请号：US16118974
申请日：2018-08-31
Applicant: NXP B.V.
Inventor： Cicero Silveira Vaucher , Sander Derksen , Erwin Janssen , Bernardus Johannes Martinus Kup
Abstract: There is disclosed an apparatus comprising a first phase-locked loop comprising: a phase detector (302, 304), arranged to receive a reference clock signal (306) and a feedback clock signal (308) and to output a frequency control signal based on a phase difference between the reference clock signal (306) and the feedback clock signal (308); a variable-frequency oscillator (312, 314) arranged to output an oscillator signal having a frequency dependent on said frequency control signal; first divider circuitry (316) for generating said feedback clock signal (308) by frequency-dividing said oscillator signal; and second divider circuitry (320) for generating an output clock signal (3220 by frequency-dividing said oscillator signal; wherein a phase relation between said first divider circuitry (316) and said second divider circuitry (320) is adjustable to delay or advance said output clock signal (322) relative to said feedback clock signal (308). The apparatus may be a radar receiver or transceiver.
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公开(公告)号：US10530372B1
公开(公告)日：2020-01-07
申请号：US15470616
申请日：2017-03-27
Applicant: MY Tech, LLC
Inventor： Tommy Yu , Avanindra Madisetti
Abstract: Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.
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公开(公告)号：US10530369B2
公开(公告)日：2020-01-07
申请号：US16522624
申请日：2019-07-25
Applicant: RichWave Technology Corp.
Inventor： Tse-Peng Chen
Abstract: A subsampling motion detector used to detect motion information of an object under measurement receives a first wireless radio frequency (RF) signal and transmits a second wireless RF signal, the first wireless RF signal being generated by reflecting the second wireless RF signal from the object. The subsampling motion detector has a high frequency oscillator for outputting a high frequency oscillation signal, a low frequency controllable oscillator for generating a low frequency oscillation signal according to a control signal, and a subsampling analog-to-digital converter (SSADC). The SSADC detects a phase difference between the high frequency oscillation signal and the low frequency oscillation signal at time periods indicated by the low frequency oscillation signal. The SSADC outputs a phase detection digital output signal according to the detected phase difference. The control signal is generated and the motion information of the object is calculated according to the phase detection digital output signal.
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公开(公告)号：US10523214B1
公开(公告)日：2019-12-31
申请号：US15965911
申请日：2018-04-28
Applicant: HQPHOTONICS INC.
Inventor： Jiang Li , Kerry Vahala
IPC: H03L7/06 , H03L5/00 , H01S3/11 , H04B10/50 , H01S3/094 , H01S3/13 , H04B10/2507 , H01S5/065 , H01S3/067 , H04B10/25 , H01S3/30
Abstract: A voltage-controlled oscillator generates a VCO output signal at frequency fM. A dual optical-frequency source generates optical signals at frequencies v1S and v2S. An electro-optic frequency divider (EOFD) generates multiple optical sidebands spaced by fM, and from two sidebands generates a beat signal at beat frequency δf. A first control circuit generates an error signal from the beat signal and a first reference signal at frequency fREF1, and couples the VCO and the EOFD in a negative feedback arrangement that stabilizes the output frequency fM. A second control circuit generates an error signal from the frequency-divided output signal and a second reference signal at frequency fREF2, and couples the VCO and one or both of the dual source or the first reference signal in a negative feedback arrangement that stabilizes, or compensates for fluctuations of, a difference frequency v2S−v1S.
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公开(公告)号：US20190341922A1
公开(公告)日：2019-11-07
申请号：US16418777
申请日：2019-05-21
Applicant: Analog Devices, Inc.
Inventor： John Kevin Behel , Kenny Gentile , Carroll C. Speir , Matthew D. McShea , Matthew Louis Courcy , Reuben Pascal Nelson
Abstract: Aspects of this disclosure relate to adjusting a phase of a clock signal provided to a device based on a feedback signal from the device. The feedback signal can provide phase information associated with the device and/or other information associated with the device, such as temperature information. A feedback signal processor can compute a phase control signal based on the feedback signal. The phase control signal can be used to adjust the phase of the clock signal. By adjusting the phase of one or more clock signals, several devices, such as data converters, can be synchronized.
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公开(公告)号：US10411718B2
公开(公告)日：2019-09-10
申请号：US15714372
申请日：2017-09-25
Applicant: QUALCOMM Incorporated
Inventor： Karthik Nagarajan , Chenling Huang , Debesh Bhatta
IPC: H03L7/06 , H03L7/093 , H03L7/089 , H03K5/26 , H03K5/1252 , H03L7/07 , H03L7/087 , H03L7/22 , H03L7/23 , H03K5/00
Abstract: A method and apparatus for reducing the amount of jitter in a signal are disclosed. In one embodiment a feed-forward loop compares the edges of a reference clock and an input signal, converts a time difference of the compared edges into a voltage signal, and controls a time delay in a voltage controlled delay line in order to reduce or eliminate jitter.
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公开(公告)号：US10361689B2
公开(公告)日：2019-07-23
申请号：US15855039
申请日：2017-12-27
Applicant: International Business Machines Corporation
Inventor： Andreas H. A. Arp , Fatih Cilek , Michael V. Koch , Matthias Ringe
IPC: H03K3/017 , H03L7/06 , H03K19/00 , H03L7/089 , H03K5/156 , H03K5/159 , G06F1/12 , G06F1/06 , H03K5/00
Abstract: Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device corrects a clock input signal, according to a first control signal. A programmable delay circuit or a modified duty cycle correction circuit in the duty cycle correction device compensates a shift of an active clock edge in a clock output signal of the duty cycle correction circuit, according to a second control signal. A mapping circuit in the duty cycle correction device generates the second control signal by mapping a digital value of the first control signal and a digital value of the second control signal.
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公开(公告)号：US10338632B2
公开(公告)日：2019-07-02
申请号：US15516883
申请日：2015-09-15
Applicant: Ambiq Micro, Inc. , Scott Hanson , Yanning Lu
Inventor： Scott Hanson , Yanning Lu
IPC: H02M1/12 , G06F1/06 , H03L7/18 , H03L7/06 , H03L7/181 , G06F1/12 , G06F11/30 , G06F11/34 , G06F13/10 , G01R19/00 , G05F1/56 , H03K17/687 , H03M1/12 , H03L7/00 , G06F1/3237 , G06F1/3287 , G05F1/575 , G06F1/3296 , H02M3/158 , H02M1/00
Abstract: An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.
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公开(公告)号：US20190179361A1
公开(公告)日：2019-06-13
申请号：US16276931
申请日：2019-02-15
Applicant: AMBIQ MICRO, INC.
Inventor： Scott Hanson
IPC: G06F1/06 , G06F1/3287 , G06F1/3237 , H03L7/18 , H03L7/06 , H03L7/181 , G06F11/30 , G06F11/34 , G01R19/00 , H03K17/687 , G05F1/56 , G06F13/10 , H03L7/00 , H03M1/12 , G06F1/12 , H02M3/158 , G06F1/3296 , G05F1/575
Abstract: An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.
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公开(公告)号：US10304506B1
公开(公告)日：2019-05-28
申请号：US15809608
申请日：2017-11-10
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Alexander J. Branover , Benjamin Tsien , Bradley Kent , Joyce C. Wong
Abstract: Systems, apparatuses, and methods for implementing dynamic clock control to increase stutter efficiency in a memory subsystem are disclosed. A system includes at least a processor, a memory, and a communication fabric coupled to the processor and memory. The system implements a stutter mode for a first region of the fabric, with stutter mode including an idle state and an active state. Stutter efficiency is defined as the idle time divided by the sum of the active time and the idle time. Reducing the exit latency of going from the idle state to the active state increases the stutter efficiency which increases the power savings achieved by implementing the stutter mode. Since the phase-locked loop (PLL) is one of the main contributors to the exit latency, the PLL is powered down and one or more bypass clocks are provided during the stutter mode.
