-
21.
公开(公告)号:US20240321758A1
公开(公告)日:2024-09-26
申请号:US18189299
申请日:2023-03-24
Inventor: Min-Yu Chen , Po-Chen Lai , Ming-Chih Yew , Shin-Puu Jeng
IPC: H01L23/538 , H01L21/48 , H01L23/00 , H01L23/498 , H01L25/065 , H10B80/00
CPC classification number: H01L23/5386 , H01L21/4853 , H01L21/486 , H01L23/49827 , H01L23/5385 , H01L24/16 , H01L25/0655 , H10B80/00 , H01L21/6835 , H01L23/49833 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2221/68345 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/81192 , H01L2224/81815 , H01L2224/83102 , H01L2224/92125
Abstract: A composite interposer includes a local-silicon-interconnect-containing (LSI-containing) interposer that includes a local silicon interconnect (LSI) bridge; and an organic interposer located on the LSI-containing interposer, including redistribution dielectric layers embedding redistribution wiring interconnects and a metallic counter-deformation structure. The metallic counter-deformation structure includes a plurality of metallic via structures; a first metallic plate located on a first side of the plurality of metallic via structures; and a second metallic plate located on a second side of the plurality metallic via structures and vertically spaced from the first metallic plate.
-
公开(公告)号:US12100662B2
公开(公告)日:2024-09-24
申请号:US17127304
申请日:2020-12-18
Applicant: Intel Corporation
Inventor: Zhiguo Qian , Gerald Pasdast , Peipei Wang , Daniel Krueger , Edward Burton
IPC: H01L23/538 , H01L21/50 , H01L23/50 , H01L25/065
CPC classification number: H01L23/5381 , H01L21/50 , H01L23/50 , H01L23/5385 , H01L23/5386 , H01L25/0657
Abstract: An integrated circuit (IC) package, comprising a substrate that comprises a bridge die embedded within a dielectric. A first die comprising a first input/output (I/O) transmitter and a second die comprising a second I/O receiver and electrically coupled to the bridge die. A first signal trace and a first power conductor are within the bridge die. The first signal trace and the first power conductor are electrically coupled to the first I/O transmitter and the second I/O receiver. The first signal trace is to carry a digital signal and the first power conductor to provide a voltage for the second I/O receiver to read the digital signal.
-
公开(公告)号:US20240312920A1
公开(公告)日:2024-09-19
申请号:US18374310
申请日:2023-09-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Keunho CHOI
IPC: H01L23/538 , H01L23/00 , H01L25/18 , H10B80/00
CPC classification number: H01L23/5386 , H01L24/16 , H01L25/18 , H10B80/00 , H01L23/3128 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/13 , H01L24/17 , H01L24/32 , H01L24/33 , H01L24/73 , H01L2224/0557 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/06181 , H01L2224/08145 , H01L2224/08225 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16145 , H01L2224/16227 , H01L2224/1703 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/3303 , H01L2224/33181 , H01L2224/73204 , H01L2224/73253 , H01L2924/014 , H01L2924/1431 , H01L2924/1432 , H01L2924/1433 , H01L2924/1436 , H01L2924/1437 , H01L2924/1438
Abstract: A semiconductor package includes: a first redistribution structure having a structure including at least one first redistribution layer and at least one first insulating layer; a first semiconductor chip disposed on the first redistribution structure; a second semiconductor chip disposed on the first redistribution structure; and bumps disposed between the first redistribution structure and the first semiconductor chip and between the first redistribution structure and the second semiconductor chip, wherein the at least one first redistribution layer includes a detour redistribution line disposed so that a portion of the detour redistribution line overlaps a space between the first and second semiconductor chips, and the detour redistribution line circuitously extends across the space between the first and second semiconductor chips so as not to overlap a stress concentration region partially overlapping a portion of the space between the first and second semiconductor chips, or extends into the stress concentration region.
-
公开(公告)号:US20240312919A1
公开(公告)日:2024-09-19
申请号:US18120910
申请日:2023-03-13
Applicant: Intel Corporation
Inventor: Pezhman MONADGEMI
IPC: H01L23/538 , H01L25/00 , H01L25/065
CPC classification number: H01L23/5386 , H01L25/0655 , H01L25/50 , H01L23/5381 , H01L24/13 , H01L24/16 , H01L2224/13147 , H01L2224/16225 , H01L2924/1432 , H01L2924/1434
Abstract: Embodiments disclosed herein include a multi-die module. In an embodiment, the multi-die module comprises an interposer, where the interposer comprises a first region and a second region. In an embodiment, the first region is spaced apart from the second region by a saw street. In an embodiment, a first die is over the interposer, where the first die is positioned over the saw street. In an embodiment, a second die is adjacent to a first end of the first die, and a third die is adjacent to a second end of the first die opposite from the first end.
-
公开(公告)号:US12094775B2
公开(公告)日:2024-09-17
申请号:US18081047
申请日:2022-12-14
Inventor: Sidlgata V. Sreenivasan , Paras Ajay , Aseem Sayal , Ovadia Abed , Mark McDermott , Jaydeep Kulkarni , Shrawan Singhal
IPC: H01L21/768 , H01L23/00 , H01L23/48 , H01L23/538 , H01L23/544 , H01L25/00 , H01L25/065 , H01L27/06
CPC classification number: H01L21/76898 , H01L23/481 , H01L23/5386 , H01L23/544 , H01L24/83 , H01L24/95 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/32145 , H01L2224/8013 , H01L2224/95001 , H01L2225/06544 , H01L2924/1437
Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).
-
公开(公告)号:US20240304560A1
公开(公告)日:2024-09-12
申请号:US18520743
申请日:2023-11-28
Inventor: Kazuki KUWATA , Hiroshi ISHINO , Takeshi ENDO , Yoshitaka KATO
CPC classification number: H01L23/5386 , H01L21/56 , H01L21/60 , H01L23/3121 , H01L24/81 , H01L24/95 , H01L25/16 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/16245 , H01L2224/32225 , H01L2224/73253 , H01L2224/81191 , H01L2224/95 , H01L2924/10272 , H01L2924/13055 , H01L2924/13091 , H01L2924/1426
Abstract: A semiconductor device includes a first lead wire connected to a first connection target; a second lead wire connected to a second connection target; and a sealing resin that seals the first connection target, the second connection target, the first lead wire, and the second lead wire. The first lead wire includes a first connection portion connected to the first connection target, a first top portion exposed from the sealing resin, and a first standing portion connecting the first connection portion and the first top portion. The second lead wire includes a second connection portion connected to the second connection target, a second top portion exposed from the sealing resin, and a second standing portion connecting the second connection portion and the second top portion. The first top portion and the second top portion are disposed to face each other.
-
公开(公告)号:US20240297087A1
公开(公告)日:2024-09-05
申请号:US18115840
申请日:2023-03-01
Inventor: Sheng-Kai CHANG , Chih-Kang Han , Leo Li , Lieh-Chuan Chen , Chien-Li Kuo
IPC: H01L23/16 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/498 , H01L23/538 , H01L25/065
CPC classification number: H01L23/16 , H01L21/4853 , H01L21/561 , H01L21/565 , H01L21/568 , H01L23/3128 , H01L23/3135 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L23/5386 , H01L25/0655 , H01L21/563 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/96 , H01L24/97 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/96 , H01L2224/97 , H01L2924/1011
Abstract: A package module includes an interposer, a plurality of semiconductor dies on the interposer, a module stiffener on the interposer adjacent to the plurality of semiconductor dies, and a molding material layer on the interposer around the plurality of semiconductor dies and the module stiffener.
-
公开(公告)号:US12080654B2
公开(公告)日:2024-09-03
申请号:US18197245
申请日:2023-05-15
Applicant: LG INNOTEK CO., LTD.
Inventor: Jun Young Lim , Hyung Kyu Yoon , Sung Min Chae
IPC: H01L23/538 , H01L23/00 , H01L23/498 , H01L25/16 , H01L25/18
CPC classification number: H01L23/5387 , H01L23/49866 , H01L23/5386 , H01L24/16 , H01L25/16 , H01L25/18 , H01L2224/16227
Abstract: A flexible circuit board according to an embodiment of the present invention comprises: a substrate; a first wiring pattern layer disposed on a first surface of the substrate; a second wiring pattern layer disposed on a second surface opposite the first surface of the substrate; a first dummy pattern part disposed on the second surface of the substrate on which the second wiring pattern layer is not disposed; a first protection layer disposed on the first wiring pattern layer; and a second protection layer disposed on the second wiring pattern layer and the first dummy pattern part, wherein at least a part of the first dummy pattern part overlaps with the first wiring pattern layer in a vertical direction.
-
公开(公告)号:US20240290702A1
公开(公告)日:2024-08-29
申请号:US18655879
申请日:2024-05-06
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dongjoon OH , Junyun KWEON , Jumyong PARK , Jin Ho AN , Chungsun LEE , Hyunsu HWANG
IPC: H01L23/498 , H01L23/00 , H01L23/31 , H01L23/538 , H01L25/10
CPC classification number: H01L23/49822 , H01L23/3128 , H01L23/5386 , H01L23/5389 , H01L24/16 , H01L25/105 , H01L2224/16227
Abstract: Disclosed are interconnection structures and semiconductor packages. The interconnection structure includes a first dielectric layer and a first hardmask pattern that are sequentially stacked, and a first interconnection pattern that penetrates the first hardmask pattern and the first dielectric layer. The first hardmask pattern includes a dielectric material having an etch selectivity with respect to the first dielectric layer. The first interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other. The first pad part vertically overlaps the via part. The line part extends from the first pad part. A level of a bottom surface of the first pad part is lower than a level of a bottom surface of the line part.
-
公开(公告)号:US12074148B2
公开(公告)日:2024-08-27
申请号:US18074027
申请日:2022-12-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Fong-Yuan Chang , Po-Hsiang Huang , Lee-Chung Lu , Jyh Chwen Frank Lee , Yii-Chian Lu , Yu-Hao Chen , Keh-Jeng Chang
IPC: H01L25/10 , H01L21/48 , H01L21/56 , H01L21/683 , H01L23/00 , H01L23/31 , H01L23/367 , H01L23/538 , H01L25/00 , H01L25/065
CPC classification number: H01L25/105 , H01L21/4853 , H01L21/4857 , H01L21/4871 , H01L21/565 , H01L21/6835 , H01L23/3128 , H01L23/367 , H01L23/5383 , H01L23/5386 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L25/0657 , H01L25/50 , H01L2221/68372 , H01L2224/214 , H01L2225/0651 , H01L2225/06586 , H01L2225/06589 , H01L2225/1035 , H01L2225/1058 , H01L2225/1094
Abstract: A semiconductor package includes a first package component comprising: a first semiconductor die; a first encapsulant around the first semiconductor die; and a first redistribution structure electrically connected to the semiconductor die. The semiconductor package further includes a second package component bonded to the first package component, wherein the second package component comprises a second semiconductor die; a heat spreader between the first semiconductor die and the second package component; and a second encapsulant between the first package component and the second package component, wherein the second encapsulant has a lower thermal conductivity than the heat spreader.