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公开(公告)号：US20230071705A1
公开(公告)日：2023-03-09
申请号：US17470141
申请日：2021-09-09
Applicant: Western Digital Technologies, Inc.
Inventor： Dudy David Avraham , Ran Zamir , Judah Gamliel Hahn
IPC: G06F3/06
Abstract: A data storage device includes a memory device including a plurality of endurance groups and a controller coupled to the memory device. The controller is configured to allocate tokens to the plurality of endurance groups, determine whether endurance group has sufficient tokens to perform an operation, and either deny the operation or approve the operation. The operation is selected from the group consisting of: garbage collection, relocation of data, and read scrubbing. Each operation has the same or different cost as another operation. The controller is further configured to set thresholds for each endurance group of the plurality of endurance groups and adjust a threshold for one or more endurance groups of the plurality of endurance groups. The controller is further configured to determine whether the operation will breach quality of service for other endurance groups.
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公开(公告)号：US11538534B1
公开(公告)日：2022-12-27
申请号：US17342183
申请日：2021-06-08
Applicant: Western Digital Technologies, Inc.
Inventor： Ran Zamir , Alexander Bazarsky , Eran Sharon
IPC: G06F12/00 , G11C16/26 , G06F11/10 , G11C29/52 , G06F3/06 , G11C16/34 , G11C11/56 , G11C16/04 , H01L25/065
Abstract: Calibration of soft bit reference levels in a non-volatile memory system is disclosed. When the soft bit reference levels are to be calibrated, encoded data is read from a group of the memory cells. The encoded data is decoded and error corrected. Therefore, the original data that was programmed into the memory cells is recovered. The group of memory cells are sensed at candidate soft bit reference levels, and possibly other reference levels. For each candidate soft bit reference level, mutual information between the original programmed data and the data for that candidate soft bit reference level is determined. The mutual information serves as a good measure for how well the candidate soft bit reference level will aid in decoding the data. In an aspect, a soft bit reference level having the highest mutual information out of several candidates is selected as the calibrated soft bit reference level.
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23.发明授权
公开(公告)号：US11507835B2
公开(公告)日：2022-11-22
申请号：US16896134
申请日：2020-06-08
Applicant: Western Digital Technologies, Inc.
Inventor： Alexander Bazarsky , Ran Zamir
Abstract: Methods and apparatus are disclosed for managing the storage of dynamic neural network data within bit-addressable memory devices, such phase change memory (PCM) arrays or other storage class memory (SCM) arrays. In some examples, a storage controller determines an expected amount of change within data to be updated. If the amount is below a threshold, an In-place Write is performed using bit-addressable writes via individual SET and RESET pulses. Otherwise, a modify version of an In-place Write is performed where a SET pulse is applied to preset a portion of memory to a SET state so that individual bit-addressable writes then may be performed using only RESET pulses to encode the updated data. In other examples, a storage controller separately manages static and dynamic neural network data by storing the static data in a NAND-based memory array and instead storing the dynamic data in a SCM array.
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公开(公告)号：US11455208B2
公开(公告)日：2022-09-27
申请号：US17171746
申请日：2021-02-09
Applicant: Western Digital Technologies, Inc.
Inventor： Ran Zamir , Omer Fainzilber , David Avraham , Eran Sharon
Abstract: A memory controller including, in one implementation, a memory interface and a control circuit. The memory interface is configured to receive a punctured codeword read from a non-volatile memory. The control circuit is configured to determine error probability values for a plurality of check nodes associated with a punctured bit included in the punctured codeword. The control circuit is also configured to determine an error probability value for the punctured bit based on the error probability values for the plurality of check nodes associated with the punctured bit and a variable degree associated with the punctured bit. The control circuit is further configured to determine a log likelihood ratio (LLR) value for the punctured bit based on the error probability value for the punctured bit. The control circuit is also configured to decode the punctured codeword using the LLR value for the punctured bit.
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公开(公告)号：US20220300369A1
公开(公告)日：2022-09-22
申请号：US17202601
申请日：2021-03-16
Applicant: Western Digital Technologies, Inc.
Inventor： Eran Sharon , Idan Goldenberg , Idan Alrod , Ran Zamir , Alexander Bazarsky
IPC: G06F11/10 , G06F11/07 , G06F12/0882
Abstract: A storage system generates a low-density parity check (LDPC) code from a plurality of subcodes. The storage system stores each subcode in a different page of a word line in the memory. The subcode can be stored in one plane in the memory or across multiple planes. When the subcodes are stored across multiple planes, they can be stored in a checkboard pattern.
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公开(公告)号：US20220116053A1
公开(公告)日：2022-04-14
申请号：US17177940
申请日：2021-02-17
Applicant: Western Digital Technologies, Inc.
Inventor： Ran Zamir , Eran Sharon , Idan Alrod , Alexander Bazarsky , Yan Li , A Harihara Sravan
Abstract: A memory includes, in one embodiment, one or more storage elements; read/write circuitry; and compressed bit circuitry. The read/write circuitry is configured to read a set of hard bits from the one or more storage elements, and sense a set of soft bits while reading the set of hard bits from the one or more storage elements, the set of soft bits having a first fixed size, and the set of soft bits indicating a reliability of the set of hard bits. The compressed soft bit circuitry is configured to generate, with a fixed size soft bit lossy compression algorithm, a fixed size compressed soft bits by compressing the set of soft bits, the fixed size compressed soft bits having a second fixed size that is smaller than the first fixed size, and output the fixed size compressed soft bits to a memory-to-controller bus.
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公开(公告)号：US11158369B2
公开(公告)日：2021-10-26
申请号：US16232639
申请日：2018-12-26
Applicant: Western Digital Technologies, Inc.
Inventor： Eran Sharon , Alon Marcu , Shay Benisty , Judah Gamliel Hahn , Idan Alrod , Alexander Bazarsky , Ariel Navon , Ran Zamir
IPC: G11C11/56 , H03K19/21 , G06F9/30 , G11C8/16 , G11C11/065 , H03K19/1776
Abstract: The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.
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公开(公告)号：US20210286623A1
公开(公告)日：2021-09-16
申请号：US16815860
申请日：2020-03-11
Applicant: Western Digital Technologies, Inc.
Inventor： Ariel Navon , Ran Zamir , Shay Benisty
Abstract: A storage system and method for implementing an encoder, decoder, and/or buffer using a field programmable gate array are provided. In one embodiment, a storage system is provided with a field programmable gate array and a memory that stores sets of instruction code for the field programmable gate array. The sets of instruction code can be for different error decoder implementations, for providing an additional encoder and/or decoder, or for implementing a host memory buffer or a controller memory buffer.
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公开(公告)号：US20200304149A1
公开(公告)日：2020-09-24
申请号：US16357522
申请日：2019-03-19
Applicant: Western Digital Technologies, Inc.
Inventor： Ran Zamir , Eran Sharon , Idan Goldenberg , Dudy David Avraham
Abstract: A method for punctured bit estimation includes receiving a punctured codeword. The method further includes generating a reconstructed codeword using the punctured codeword and at least one punctured bit having a default logic value. The method further includes generating a syndrome vector for the reconstructed codeword. The method further includes determining, using the syndrome vector, a number of unsatisfied parity-checks for the at least one punctured bit. The method further includes determining, for the at least one punctured bit, a bit value using, at least, the number of unsatisfied parity-checks associated with the at least one punctured bit.
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公开(公告)号：US10418097B2
公开(公告)日：2019-09-17
申请号：US15822798
申请日：2017-11-27
Applicant: Western Digital Technologies, Inc.
Inventor： David Avraham , Eran Sharon , Ran Zamir , Alexander Bazarsky
Abstract: Read reference levels are used to distinguish different data states for information stored in non-volatile memory. A storage system recalibrates its read reference levels, to maintain accuracy of the read process, by sensing samples of data for different test read reference levels and using those samples to determine an improved set of read reference levels. At least a subset of the test read reference levels used for the samples are dynamically and adaptively chosen based on indications of error for previous samples.
