公开(公告)号：US10515928B2

公开(公告)日：2019-12-24

申请号：US14167647

申请日：2014-01-29

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  Anis Fauzi bin Abdul Aziz ,  Khoo Yien Sien

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/495 ,  H01L21/78 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor system (900) has a flat interposer (510) with a first surface (401a) in a first plane, a second surface (401b) in a parallel second plane, and a uniform first height (401) between the surfaces; the interposer is patterned in metallic zones separated by gaps (412, 415), the zones include metal of the first height and metal of a second height (402) smaller than the first height; an insulating material fills the gaps and the zone differences between the first and the second heights. Semiconductor chips of a first (610) and a second (611) set have first terminals attached to metallic zones of the first interposer surface while the chips of the second set have their second terminals facing away from the interposer. A first leadframe (700) is attached to the second terminals of the second set chips, and a second leadframe (800) is attached to respective metallic zones of the second interposer surface.

公开(公告)号：US09892936B2

公开(公告)日：2018-02-13

申请号：US15340837

申请日：2016-11-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Wei Fen Sueann Lim ,  Lee Han Meng@ Eugene Lee ,  Anis Fauzi Bin Abdul Aziz

IPC: H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L21/561 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49541 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49052 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8346 ,  H01L2224/85439 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/01028 ,  H01L2924/01027 ,  H01L2224/85 ,  H01L2224/83

Abstract: A semiconductor device has a leadframe with a first (401a) and a parallel second surface, and an assembly pad (410) bordered by two opposing sides, which include a plurality of through-holes (420) from the first to the second pad surface. Another pad side includes one or more elongated windows (421) between the pad surfaces. The second pad surface includes a plurality of grooves. The leadframe further has a plurality of leads (430) with opposite elongated sides castellated by indents (431). Layers (440) of bondable metals are restricted to localized areas surrounding bond spots. A semiconductor chip (450) is attached to the pad and wire-bonded (460) to the bond spots. A package (470) encapsulates the chip, wires, pad, and lead portions, and secures the leadframe into the package by filling the through-holes, windows, grooves, and indents.

公开(公告)号：US20170110408A1

公开(公告)日：2017-04-20

申请号：US14887047

申请日：2015-10-19

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  Anis Fauzi bin Abdul Aziz ,  Sueann Lim Wei Fen

IPC: H01L23/538 ,  H01L21/78 ,  H01L21/56 ,  H01L21/48 ,  H01L23/495 ,  H01L21/768

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/08 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/80 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/0579 ,  H01L2224/05839 ,  H01L2224/08245 ,  H01L2224/29009 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73251 ,  H01L2224/73265 ,  H01L2224/9222 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/35121 ,  H01L2924/3862 ,  H01L2924/00014 ,  H01L2224/291 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00 ,  H01L2924/0781 ,  H01L2924/0665 ,  H01L2224/08 ,  H01L2224/80 ,  H01L2224/48

Abstract: An integrated circuit (IC) die including a top surface and a bottom surface, a plurality of spaced apart ground connection traces positioned between the top surface and the bottom surface; with a hole in the die exposing the plurality of spaced apart ground connection traces.

公开(公告)号：US20160181122A1

公开(公告)日：2016-06-23

申请号：US14581233

申请日：2014-12-23

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  Shu Hui Ooi ,  Anis Fauzi Abdul Aziz ,  Sueann Lim Wei Fen

IPC: H01L21/48 ,  C25D17/08 ,  C25D7/00 ,  H01L23/495 ,  C25D5/02

CPC classification number: H01L21/4821 ,  C25D5/022 ,  C25D7/00 ,  C25D17/08 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/0002 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A method of making Flat No-Lead Packages with plated lead surfaces exposed on lateral faces thereof. The method includes providing a plurality of Flat No-Lead Packages having severed, unplated lead surfaces exposed on lateral faces thereof and having plated lead surfaces exposed on bottom faces thereof. The method further includes batch electroplating the severed unplated lead surfaces of the plurality of Flat No-Lead Packages.

Abstract translation: 一种制造平面无铅封装的方法，其电镀引线表面暴露在其侧面上。 该方法包括提供多个平面无铅封装，其具有暴露在其侧面上的切断的未镀层的引线表面，并且具有暴露在其底面上的电镀引线表面。 该方法还包括批量电镀多个扁平无铅封装的切断的未镀层的引线表面。

公开(公告)号：US09275983B2

公开(公告)日：2016-03-01

申请号：US14706052

申请日：2015-05-07

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  Anis Fauzi bin Abdul Aziz ,  Yien Sien Khoo

IPC: H04L21/00 ,  H01L25/00 ,  H01L23/495 ,  H01L21/56 ,  H01L23/498 ,  H01L25/16 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49531 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49589 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/165 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/8121 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83815 ,  H01L2224/97 ,  H01L2924/12 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/81

Abstract: A method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe.

Abstract translation: 一种制造集成电路（IC）封装的方法，所述集成电路（IC）封装包括将裸片电连接和物理附接到插入器，将所述插入件附接到底部引线框架，将分立电路部件附接到所述插入器并将顶部引线框架附接到所述底部引线框架。

公开(公告)号：US20150228581A1

公开(公告)日：2015-08-13

申请号：US14691660

申请日：2015-04-21

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  Sueann Lim Wei Fen ,  Sarel Bin Ismail

IPC: H01L23/532 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/495 ,  H01L23/544

CPC classification number: H01L23/49541 ,  H01L21/4821 ,  H01L21/4842 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/5328 ,  H01L23/544 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L2223/54426 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/27312 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2224/83862 ,  H01L2224/85439 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A method of making an integrated circuit (“IC”) device includes forming a lead frame in a lead frame strip. Only portions of the lead frame are plated with a conductor. A die pad is attached to an unplated portion of said lead frame.

Abstract translation: 一种制造集成电路（“IC”）器件的方法包括在引线框条中形成引线框架。 只有引线框架的一部分镀有导体。 芯片焊盘连接到所述引线框架的未镀层部分。