Abstract:
A droplet generator for extreme ultraviolet (EUV) exposure device includes a nozzle body with an inclined portion, the nozzle body with the inclined portion having a nozzle shape to discharge a target material in a liquid state, a gas supply pipe, at least a portion of the gas supply pipe being in an internal space of the nozzle body and of the inclined portion, and the gas supply pipe to discharge gas toward the target material in the liquid state, a target material supply unit connected to the nozzle body, the target material supply unit including a first valve, a gas supply unit connected to the gas supply pipe, the gas supply unit including a second valve, and a control unit connected to the first and second valves to control a supply amount of the target material and the gas.
Abstract:
An extreme ultraviolet exposure system includes an exposure chamber having an internal space, upper and lower electrostatic chucks, a power supply, a light source, and a mask. The upper electrostatic chuck includes first and second electrodes that are adjacent to one another and that generate an electric field of different polarities, respectively, to provide an electrostatic force. The mask is attachable to the lower surface of the upper electrostatic chuck by the electrostatic force. The mask has a metal thin film pattern including a first region in which a metal thin film that shields the electric field, and a second region in which the metal thin film is not disposed and through which the electric field is transmitted. When the mask is attached, the electric field transmitted through the second region applies an attractive force or a repulsive force to charged particles in the exposure chamber.
Abstract:
A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.
Abstract:
A semiconductor memory device includes a bit line sense amplifier, a first column select gate, and a second column select gate. The bit line sense amplifier senses an electric potential difference between a bit line and a complementary bit line during a sensing operation for memory cells. The first column select gate transfers an electric potential on the bit line to a local sense amplifier based on a column select signal. The second column select gate transfers an electric potential on the complementary bit line to the local sense amplifier based on the column select signal. The first and second column select gates have different current drive abilities to compensate a difference in bit line interconnection resistance.