公开(公告)号：US20240045336A1

公开(公告)日：2024-02-08

申请号：US18133118

申请日：2023-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sookyung KIM ,  Chan HWANG ,  Jonghyun JUNG ,  Moosong LEE

IPC: G03F7/20 ,  G03F7/004

CPC classification number: G03F7/2004 ,  G03F7/2022 ,  G03F7/0045

Abstract: A method for forming a resist pattern is disclosed. According to the method, a photosensitive layer is formed on a substrate by using an inorganic photoresist. The photosensitive layer is irradiated with a deep ultraviolet (DUV) light. The photosensitive layer is irradiated with an extreme ultraviolet (EUV) light after the irradiation of the DUV light. The photosensitive layer exposed to the EUV light is heated. The heated photosensitive layer is developed.

公开(公告)号：US20210333701A1

公开(公告)日：2021-10-28

申请号：US16952844

申请日：2020-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doogyu LEE ,  Seungyoon LEE ,  Jeongjin LEE ,  Chan HWANG

IPC: G03F1/24 ,  G03F7/20 ,  H01L21/027

Abstract: Provided are an extreme ultraviolet (EUV) exposure apparatus for improving an overlay error in a EUV exposure process, and an overlay correction method and a semiconductor device fabricating method using the exposure apparatus. The EUV exposure apparatus includes an EUV light source; a first optical system configured to emit EUV light from the EUV light source to an EUV mask; a second optical system configured to emit EUV light reflected from the EUV mask to a wafer; a mask stage; a wafer stage; and a control unit configured to control the mask stage and the wafer stage, wherein, based on a correlation between a first overlay parameter, which is one of parameters of overlay errors between layers on the wafer, and a second overlay parameter, which is another parameter, the first overlay parameter is corrected through correction of the second overlay parameter.

公开(公告)号：US20210116803A1

公开(公告)日：2021-04-22

申请号：US16886237

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo-Yong JUNG ,  Jinsun KIM ,  Seungyoon LEE ,  Jeongjin LEE ,  Chan HWANG

IPC: G03F1/70 ,  G03F1/36 ,  H01L21/66 ,  H01L21/027 ,  G03F7/20

Abstract: An overlay correction method may include obtaining a first central line of a lower pattern on a substrate, forming a photoresist pattern on the lower pattern, obtaining an ADI overlay value corresponding to a first distance between a second central line of an upper flat surface of the lower pattern and a third central line of the photoresist pattern, obtaining an asymmetrical overlay value corresponding to a second distance between the first and second central lines, form an upper pattern using the photoresist pattern, obtaining an ACI overlay value corresponding to a third distance between the first central line and a fourth central line of the upper pattern, subtracting the ADI overlay value from the ACI overlay value to obtain a first overlay skew value, and adding the asymmetrical overlay value to the first overlay skew value to obtain a second overlay skew value.

公开(公告)号：US20190363054A1

公开(公告)日：2019-11-28

申请号：US16361546

申请日：2019-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAEHONG MIN ,  Chan HWANG

IPC: H01L23/544 ,  H01L45/00

Abstract: A method of fabricating a semiconductor device includes providing a substrate including a first region and a second region. The method includes forming a first layer on the substrate. The first layer has a first hole on the first region and a second hole on the second region. The method includes forming a second layer in the first hole and the second hole. The method includes forming a mask pattern on the second region of the substrate. The method includes polishing the second layer to form a pattern in the first hole and an overlay key pattern in the second hole. A top surface of the overlay key pattern is further from the substrate than a top surface of the pattern in the first hole.

公开(公告)号：US20180175043A1

公开(公告)日：2018-06-21

申请号：US15826944

申请日：2017-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soon-mok HA ,  Jae-hee KIM ,  Chan HWANG ,  Jong-hyuk KIM

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L27/10855 ,  H01L21/0273 ,  H01L21/31127 ,  H01L21/31144 ,  H01L27/10817 ,  H01L28/87 ,  H01L28/91

Abstract: A method of forming a micro-pattern including forming a mold layer and a supporting material layer on a substrate, patterning the mold layer and the supporting material layer to form recess patterns, forming conductor patterns in the recess patterns, removing a portion of an upper portion of the supporting material layer for causing upper portions of the conductor patterns to protrude, forming a block copolymer layer on the supporting material layer, processing the block copolymer layer to phase-separate the block copolymer layer into a plurality of block parts, selectively removing some of the phase-separated plurality of block parts, and removing the supporting material layer to expose the mold layer at a position corresponding to each of the removed block parts may be provided.