DEBUG SYSTEM, AND RELATED INTEGRATED CIRCUIT AND METHOD
    21.
    发明申请
    DEBUG SYSTEM, AND RELATED INTEGRATED CIRCUIT AND METHOD 有权
    调试系统及相关集成电路及方法

    公开(公告)号:US20140095932A1

    公开(公告)日:2014-04-03

    申请号:US14038501

    申请日:2013-09-26

    CPC classification number: G06F11/27 G06F11/2236 G06F11/3648

    Abstract: A system includes a processor and a plurality of circuits connected through an interconnection network, wherein associated to each circuit is a respective communication interface configured for exchanging data between the respective circuit and the interconnection network. In particular, a debug unit is associated with each communication interface. Each debug unit is configurable as a data-insertion point, wherein the debug unit transmits data by means of the respective communication interface to the interconnection network, or each debug unit is configurable as a data-reception point, wherein the debug unit receives data by means of the respective communication interface from the interconnection network.

    Abstract translation: 系统包括处理器和通过互连网络连接的多个电路,其中与每个电路相关联的是相应的通信接口,被配置为在相应电路和互连网络之间交换数据。 特别地,调试单元与每个通信接口相关联。 每个调试单元可配置为数据插入点,其中调试单元通过相应的通信接口将数据发送到互连网络,或者每个调试单元可配置为数据接收点,其中调试单元通过 来自互连网络的相应通信接口的装置。

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