Methods and apparatus related to a modular switch architecture
    21.
    发明授权
    Methods and apparatus related to a modular switch architecture 有权
    与模块化交换架构相关的方法和设备

    公开(公告)号:US08804711B2

    公开(公告)日:2014-08-12

    申请号:US12345502

    申请日:2008-12-29

    IPC分类号: H04L12/58 H04L12/56

    CPC分类号: H04L49/15 H04L49/10 H04L49/45

    摘要: In some embodiments, an apparatus includes a first housing, a second housing and at least one cable. The first housing includes a first interface card of a switch fabric. The second housing includes a second interface card of the switch fabric and a third interface card of the switch fabric. The second interface card of the switch fabric is operatively and physically coupled to the third interface card of the switch fabric via a midplane. The second interface card defines a plane that is nonparallel to the a plane defined by the third interface card and a plane defined by the midplane. The plane defined by the third interface card is nonparallel to the plane defined by the second interface card and the plane defined by the midplane. The cable is configured to operatively couple the first interface card to the second interface card.

    摘要翻译: 在一些实施例中,装置包括第一壳体,第二壳体和至少一个电缆。 第一壳体包括交换结构的第一接口卡。 第二壳体包括交换结构的第二接口卡和交换结构的第三接口卡。 交换结构的第二接口卡经由中间平面操作和物理地耦合到交换结构的第三接口卡。 第二接口卡限定了与第三接口卡所定义的平面不平行的平面和由中平面限定的平面。 由第三接口卡定义的平面与由第二接口卡定义的平面和由中平面限定的平面不平行。 电缆被配置为将第一接口卡可操作地耦合到第二接口卡。

    Methods and apparatus related to flow control within a data center switch fabric
    22.
    发明授权
    Methods and apparatus related to flow control within a data center switch fabric 失效
    与数据中心交换机结构中的流量控制有关的方法和设备

    公开(公告)号:US08755396B2

    公开(公告)日:2014-06-17

    申请号:US12495361

    申请日:2009-06-30

    IPC分类号: H04L12/28

    摘要: In one embodiment, an apparatus includes a switch core that has a multi-stage switch fabric physically distributed among a set of chassis. The multi-stage switch fabric has a set of input buffers and a set of output ports. The switch core can be configured to be coupled to a set of edge devices. The apparatus can also include a controller implemented in hardware without software during operation and with software during configuration and monitoring. The controller can be coupled to the set of input buffers and the set of output ports. The controller can be configured to send a flow control signal to an input buffer from the set of input buffers when congestion at an output port from the set of output ports is predicted and before congestion in the switch core occurs.

    摘要翻译: 在一个实施例中,装置包括交换机核心,其具有物理上分布在一组机箱中的多级交换机结构。 多级交换结构具有一组输入缓冲器和一组输出端口。 交换机核心可以被配置为耦合到一组边缘设备。 该装置还可以包括在操作期间以软件实现的控制器,并且在配置和监视期间具有软件。 控制器可以耦合到一组输入缓冲器和一组输出端口。 控制器可以被配置为在预测来自该组输出端口的输出端口处的拥塞并且在交换机核心发生拥塞之前从该组输入缓冲器向输入缓冲器发送流控制信号。

    Methods and apparatus related to a low cost data center architecture
    24.
    发明授权
    Methods and apparatus related to a low cost data center architecture 有权
    与低成本数据中心架构相关的方法和设备

    公开(公告)号:US08340088B2

    公开(公告)日:2012-12-25

    申请号:US12558130

    申请日:2009-09-11

    IPC分类号: H04L12/56

    摘要: In one embodiment, an apparatus can include a first edge device that can have a packet processing module. The first edge device can be configured to receive a packet. The packet processing module of the first edge device can be configured to produce cells based on the packet. A second edge device can have a packet processing module configured to reassemble the packet based on the cells. A multi-stage switch fabric can be coupled to the first edge device and the second edge device. The multi-stage switch fabric can define a single logical entity. The multi-stage switch fabric can have switch modules. Each switch module from the switch modules can have a shared memory device. The multi-stage switch fabric can be configured to switch the cells so that the cells are sent to the second edge device.

    摘要翻译: 在一个实施例中,装置可以包括可以具有分组处理模块的第一边缘设备。 第一边缘设备可以被配置为接收分组。 第一边缘设备的分组处理模块可以被配置为基于分组来生成单元。 第二边缘设备可以具有配置成基于小区重新组合分组的分组处理模块。 多级交换结构可以耦合到第一边缘设备和第二边缘设备。 多级交换结构可以定义单个逻辑实体。 多级交换结构可以具有交换机模块。 交换机模块的每个交换机模块都可以具有共享存储设备。 多级交换结构可以被配置为切换小区,使得小区被发送到第二边缘设备。

    METHODS AND APPARATUS RELATED TO LOSSLESS OPERATION WITHIN A DATA CENTER
    25.
    发明申请
    METHODS AND APPARATUS RELATED TO LOSSLESS OPERATION WITHIN A DATA CENTER 审中-公开
    与数据中心无关操作相关的方法和装置

    公开(公告)号:US20100061367A1

    公开(公告)日:2010-03-11

    申请号:US12495344

    申请日:2009-06-30

    IPC分类号: H04L12/56

    摘要: In one embodiment, an apparatus includes a switch core that defines a single logical entity and has a multi-stage switch fabric that has a set of stages physically distributed across a set of chassis. The set of stages collectively has a set of ingress ports and a set of egress ports. The switch core can be configured to be coupled to a set of peripheral processing devices via the set of ingress ports and the set of egress ports. The switch core can be configured to admit a set of cells associated with a packet into an ingress port from the set of ingress ports when delivery of the set of cells can be substantially guaranteed without loss through the multi-stage switch fabric.

    摘要翻译: 在一个实施例中,装置包括交换机核心,其定义单个逻辑实体并且具有多级交换机结构,其具有物理上分布在一组机箱上的一组级。 这些阶段集合有一组入口端口和一组出口端口。 交换机核心可以被配置为经由一组入口端口和一组出口端口耦合到一组外围处理设备。 交换机核心可以被配置为可以基本上保证小区集合的传送,而不会通过多级交换结构的丢失,从一组入口端口接收与分组相关联的一组小区到入口端口。

    METHODS AND APPARATUS RELATED TO FLOW CONTROL WITHIN A DATA CENTER SWITCH FABRIC
    26.
    发明申请
    METHODS AND APPARATUS RELATED TO FLOW CONTROL WITHIN A DATA CENTER SWITCH FABRIC 失效
    与数据中心开关织物中的流量控制相关的方法和装置

    公开(公告)号:US20100061241A1

    公开(公告)日:2010-03-11

    申请号:US12495361

    申请日:2009-06-30

    IPC分类号: H04J1/16 H04L12/56

    摘要: In one embodiment, an apparatus includes a switch core that has a multi-stage switch fabric physically distributed among a set of chassis. The multi-stage switch fabric has a set of input buffers and a set of output ports. The switch core can be configured to be coupled to a set of edge devices. The apparatus can also include a controller implemented in hardware without software during operation and with software during configuration and monitoring. The controller can be coupled to the set of input buffers and the set of output ports. The controller can be configured to send a flow control signal to an input buffer from the set of input buffers when congestion at an output port from the set of output ports is predicted and before congestion in the switch core occurs.

    摘要翻译: 在一个实施例中,装置包括交换机核心,其具有物理上分布在一组机箱中的多级交换机结构。 多级交换结构具有一组输入缓冲器和一组输出端口。 交换机核心可以被配置为耦合到一组边缘设备。 该装置还可以包括在操作期间以软件实现的控制器,并且在配置和监视期间具有软件。 控制器可以耦合到一组输入缓冲器和一组输出端口。 控制器可以被配置为在预测来自该组输出端口的输出端口处的拥塞并且在交换机核心发生拥塞之前从该组输入缓冲器向输入缓冲器发送流控制信号。

    Ordering write bursts to memory
    29.
    发明授权
    Ordering write bursts to memory 有权
    将写入脉冲排序到存储器

    公开(公告)号:US08327057B1

    公开(公告)日:2012-12-04

    申请号:US11829634

    申请日:2007-07-27

    IPC分类号: G06F12/02

    摘要: A device may receive requests intended for a memory that includes a number of banks, determine a number of the requests intended for each of the banks, determine an order for the requests based on the determined number of the requests intended for each of the banks, and send one of the requests to the memory based on the determined order.

    摘要翻译: 设备可以接收针对包括多个银行的存储器的请求,确定针对每个银行的请求的数量,基于确定的针对每个银行的请求的确定的数量来确定请求的顺序, 并根据确定的顺序将一个请求发送到存储器。

    Banked memory arbiter for control memory
    30.
    发明授权
    Banked memory arbiter for control memory 有权
    用于控制存储器的存储器仲裁器

    公开(公告)号:US08285914B1

    公开(公告)日:2012-10-09

    申请号:US11829648

    申请日:2007-07-27

    IPC分类号: G06F12/00

    摘要: A device includes a memory that includes a number of banks. The device receives requests for accessing the memory, determines the banks to which the requests are intended, determines one or more of the banks that are available, selects one or more of the requests to send to the memory based on the one or more of the banks that are available and have a request to be serviced, and sends the selected one or more requests to the memory.

    摘要翻译: 一种设备包括包含多个存储体的存储器。 该设备接收访问存储器的请求,确定要求请求的存储体,确定可用存储体中的一个或多个存储体,基于一个或多个存储器中的一个或多个来选择发送到存储器的一个或多个请求 可用的存储体并且具有要被服务的请求,并且将所选择的一个或多个请求发送到存储器。