公开(公告)号：US20190051650A1

公开(公告)日：2019-02-14

申请号：US16078675

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Peter G. Tolchinsky ,  Roza Kotlyar ,  Valluri R. Rao

IPC: H01L27/092 ,  H01L29/20 ,  H01L29/205 ,  H01L29/16 ,  H01L29/06 ,  H01L29/778 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8258 ,  H01L29/66 ,  H01L23/544 ,  H01L23/498

CPC classification number: H01L27/0922 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/28264 ,  H01L21/823807 ,  H01L21/8258 ,  H01L23/49844 ,  H01L23/544 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2223/54493 ,  H04B1/38

Abstract: This disclosure pertains to a gallium nitride transistor that is formed in a trench etched into a silicon substrate. A gallium nitride layer is on the trench of the silicon substrate. A source electrode and a drain electrode reside on the gallium nitride layer. A gate electrode resides on the gallium nitride layer between the source electrode and the drain electrode. A first polarization layer resides on the gallium nitride layer between the source electrode and the gate electrode, and a second polarization layer resides on the gallium nitride layer between the gate electrode and the drain electrode. The silicon substrate can include a silicon 111 substrate.

公开(公告)号：US10153372B2

公开(公告)日：2018-12-11

申请号：US15117590

申请日：2014-03-27

Applicant: INTEL CORPORATION

Inventor： Stephen M. Cea ,  Roza Kotlyar ,  Harold W. Kennel ,  Glenn A. Glass ,  Anand S. Murthy ,  Willy Rachmady ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/161 ,  H01L29/165

Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

公开(公告)号：US09911835B2

公开(公告)日：2018-03-06

申请号：US15410548

申请日：2017-01-19

Applicant: Intel Corporation

Inventor： Roza Kotlyar ,  Stephen M. Cea ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Rafael Rios ,  Anurag Chaudhry ,  Thomas D. Linton, Jr. ,  Ian A. Young ,  Kelin J. Kuhn

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  H01L29/161 ,  H01L29/06 ,  H01L29/24 ,  H01L29/267 ,  H01L27/092 ,  H01L29/04 ,  H01L29/10 ,  H01L29/165 ,  H01L29/20 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66977 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/7391 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/78684 ,  H01L29/78696

Abstract: Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.

公开(公告)号：US09893149B2

公开(公告)日：2018-02-13

申请号：US14935971

申请日：2015-11-09

Applicant: Intel Corporation

Inventor： Stephen M. Cea ,  Anand S. Murthy ,  Glenn A. Glass ,  Daniel B. Aubertine ,  Tahir Ghani ,  Jack T. Kavalieros ,  Roza Kotlyar

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/165 ,  H01L29/78 ,  H01L21/762 ,  H01L29/16 ,  H01L29/161 ,  H01L29/08

CPC classification number: H01L29/1054 ,  H01L21/76224 ,  H01L29/06 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.

公开(公告)号：US09871117B2

公开(公告)日：2018-01-16

申请号：US15062007

申请日：2016-03-04

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Uday Shah ,  Roza Kotlyar ,  Charles C. Kuo

IPC: H01L31/072 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/205 ,  H01L29/739 ,  H01L29/749 ,  H01L21/02 ,  H01L21/306 ,  H01L29/49 ,  H01L29/161 ,  H01L29/201 ,  H01L29/08

CPC classification number: H01L29/66666 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4983 ,  H01L29/66356 ,  H01L29/66363 ,  H01L29/7391 ,  H01L29/749 ,  H01L29/7827 ,  H01L29/7848

Abstract: Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region disposed on a substrate, an epitaxial channel semiconductor region disposed on the source semiconductor region, an epitaxial drain semiconductor region disposed on the channel semiconductor region, and a gate electrode region surrounding sidewalls of the semiconductor channel region. A composition of at least one of the semiconductor regions varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate.

公开(公告)号：US20170012116A1

公开(公告)日：2017-01-12

申请号：US15270795

申请日：2016-09-20

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Been-Yih Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L29/775 ,  H01L29/66 ,  H01L27/088 ,  H01L29/267 ,  H01L29/06

CPC classification number: H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

Abstract translation: 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。

公开(公告)号：US20160071934A1

公开(公告)日：2016-03-10

申请号：US14935971

申请日：2015-11-09

Applicant: Intel Corporation

Inventor： Stephen M. Cea ,  Anand S. Murthy ,  Glenn A. Glass ,  Daniel B. Aubertine ,  Tahir Ghani ,  Jack T. Kavalieros ,  Roza Kotlyar

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/08

CPC classification number: H01L29/1054 ,  H01L21/76224 ,  H01L29/06 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.

公开(公告)号：US20160064520A1

公开(公告)日：2016-03-03

申请号：US14924643

申请日：2015-10-27

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L29/66 ,  H01L21/283 ,  H01L21/02 ,  H01L29/15 ,  H01L29/267

CPC classification number: H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

Abstract translation: 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。

公开(公告)号：US09219135B2

公开(公告)日：2015-12-22

申请号：US14057204

申请日：2013-10-18

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L29/775 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66 ,  H01L29/778 ,  H01L29/51

CPC classification number: H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

Abstract translation: 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。

公开(公告)号：US12230687B2

公开(公告)日：2025-02-18

申请号：US17117337

申请日：2020-12-10

Applicant: Intel Corporation

Inventor： Roza Kotlyar ,  Stephanie A. Bojarski ,  Hubert C. George ,  Payam Amin ,  Patrick H. Keys ,  Ravi Pillarisetty ,  Roman Caudillo ,  Florian Luethi ,  James S. Clarke

IPC: H01L29/49 ,  B82Y10/00 ,  B82Y30/00 ,  G06N10/00 ,  H01L29/06 ,  H01L29/15 ,  H01L29/423

Abstract: Disclosed herein are lateral gate material arrangements for quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; and a gate above the quantum well stack, wherein the gate includes a gate electrode, the gate electrode includes a first material proximate to side faces of the gate and a second material proximate to a center of the gate, and the first material has a different material composition than the second material.