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公开(公告)号：US11469290B2
公开(公告)日：2022-10-11
申请号：US17040260
申请日：2019-11-29
Inventor： Zhongyuan Wu , Yongqian Li , Can Yuan , Meng Li , Zhidong Yuan , Xuehuan Feng , Lang Liu , Dacheng Zhang
Abstract: The present disclosure relates to the field of display technologies, and provides an array substrate, a manufacturing method thereof, and a display panel. In the array substrate, a substrate is provided with a first transistor and a second transistor, a first electrode of the first transistor is electrically connected to a gate of the second transistor; a conductive layer is disposed on the substrate, and includes a first conductor portion, a first semiconductor portion, a second conductor portion that are sequentially connected along a first direction; a first gate insulating layer is disposed on a side of the conductive layer away from the substrate; a first gate layer is disposed on a side of the first gate insulating layer away from the substrate to form the gate of the second transistor; a dielectric layer is disposed on the substrate to cover a part of the first conductor portion, a part of the second conductor portion and a part of the first gate layer, and an orthographic projection of a first via hole disposed on the dielectric layer on the substrate overlaps with orthographic projections of at least a part of the first conductor portion, at least a part of the second conductor portion and the first gate layer on the substrate; and a first source/drain layer is disposed on a side of the dielectric layer away from the substrate to cover the first via hole.
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公开(公告)号：US11444132B2
公开(公告)日：2022-09-13
申请号：US16976827
申请日：2019-11-29
Inventor： Zhongyuan Wu , Yongqian Li , Can Yuan , Zhidong Yuan , Meng Li , Dacheng Zhang , Lang Liu
Abstract: A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. At least one sub-pixel includes a first transistor, a second transistor, a third transistor, and a storage capacitor. The display substrate further includes an extension portion protruding from the gate electrode of the first transistor, and the extension portion is extended from the gate electrode of the first transistor in the second direction; the extension portion is at least partially overlapped with the first electrode of the second transistor in a direction perpendicular to the base substrate and is electrically connected with the first electrode of the second transistor; in the first direction, the extension portion has a second side closest to the second capacitor electrode, and the second side is recessed in a direction away from the second capacitor electrode.
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公开(公告)号：US11296162B2
公开(公告)日：2022-04-05
申请号：US16638556
申请日：2019-09-04
Inventor： Can Yuan , Yongqian Li , Zhidong Yuan
Abstract: An array substrate includes a base substrate (1); a driving transistor (2) on the base substrate (1); an insulating layer (3) on the driving transistor (2), the insulating layer (3) comprising a via hole above a first electrode (21) of the driving transistor (2); a conductive portion (4) on the insulating layer (3); and a light emitting device (6) on the conductive portion (4) and electrically connected to the conductive portion (4). The conductive portion (4) may be electrically connected to the first electrode (21) of the driving transistor (2) through the via hole. The light emitting device (6) may be above the via hole, and an orthographic projection of the light emitting device (6) on the base substrate (1) may cover an orthographic projection of the via hole on the base substrate (1).
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公开(公告)号：US11282915B2
公开(公告)日：2022-03-22
申请号：US16963975
申请日：2019-09-10
Inventor： Can Yuan , Yongqian Li , Zhidong Yuan
IPC: G09G3/3233 , H01L27/32 , G09G3/00
Abstract: A display panel and a display device are disclosed. The display panel includes a plurality of sub-pixel units arranged in an array, and the array includes N rows and 8M columns. Sub-pixel units in each row are divided into a plurality of sub-pixel unit groups, and each sub-pixel unit group includes a first sub-pixel unit, a second sub-pixel unit, a third sub-pixel unit, a fourth sub-pixel unit, a fifth sub-pixel unit, a sixth sub-pixel unit, a seventh sub-pixel unit and an eighth sub-pixel unit which are sequentially in eight adjacent columns along a first direction.
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公开(公告)号：US11238805B2
公开(公告)日：2022-02-01
申请号：US16766450
申请日：2019-11-04
Inventor： Xuehuan Feng , Yongqian Li , Can Yuan , Meng Li , Zehua Ding , Zhidong Yuan
IPC: G09G5/00 , G09G3/3266 , G09G3/3225 , G11C19/28
Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first sub-unit and a leakage prevention circuit; the first sub-unit includes a first input circuit and a first output circuit. The first input circuit controls a level of a first node in response to a first input signal, the first output circuit provides an output signal at an output terminal under control of the level of the first node, the leakage prevention circuit is connected to the first node and a first voltage terminal, and controls a level of a leakage prevention node under control of the level of the first node, whereby a conductive path is formed between the leakage prevention node and the first voltage terminal, and a circuit connected between the first node and the leakage prevention node is turned off.
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Patent Agency Ranking
公开(公告)号：US11200861B2
公开(公告)日：2021-12-14
申请号：US17000219
申请日：2020-08-21
Inventor： Zhidong Yuan , Yongqian Li , Can Yuan
IPC: G09G3/36 , G09G3/3266 , G11C19/28
Abstract: A shift register unit includes a pull-down sustaining sub-circuit and a pull-down sub-circuit. The pull-down sustaining sub-circuit includes: a first transistor having a control electrode configured to input a pull-down sustaining signal, a first electrode connected to a first power signal terminal, and a second electrode connected to a pull-down node; a first capacitor; and a second transistor having a control electrode connected to an input signal terminal. The pull-down sub-circuit includes: a third transistor having a control electrode connected to the first terminal of the first capacitor, a first electrode connected to a pull-up node, and a second electrode connected to the second power signal terminal; a fourth transistor having a control electrode connected to the first terminal of the first capacitor, a first electrode connected to an output sub-circuit, and a second electrode connected to the second power signal terminal.
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公开(公告)号：US20210256889A1
公开(公告)日：2021-08-19
申请号：US17262775
申请日：2020-06-02
Inventor： Zhidong Yuan , Yongqian Li , Can Yuan
Abstract: An array substrate and a testing method thereof are provided. The array substrate includes a plurality of clock signal lines and a plurality of testing terminals. As at least two of the plurality of clock signal lines may be connected to a same testing terminal, as compared with the arrangement of the related art in which one clock signal line is connected to one testing terminal, the array substrates provided by the embodiments of the present disclosure only need to have less testing terminals, and correspondingly, the testing device that is connected to the testing terminals of the array substrate provided by the embodiments of the present disclosure may contain less pins. Therefore, the testing device can have a relatively low production cost and a relatively small volume.
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公开(公告)号：US20210233982A1
公开(公告)日：2021-07-29
申请号：US16638556
申请日：2019-09-04
Inventor： Can Yuan , Yongqian Li , Zhidong Yuan
Abstract: An array substrate includes a base substrate (1); a driving transistor (2) on the base substrate (1); an insulating layer (3) on the driving transistor (2), the insulating layer (3) comprising a via hole above a first electrode (21) of the driving transistor (2); a conductive portion (4) on the insulating layer (3); and a light emitting device (6) on the conductive portion (4) and electrically connected to the conductive portion (4). The conductive portion (4) may be electrically connected to the first electrode (21) of the driving transistor (2) through the via hole. The light emitting device (6) may be above the via hole, and an orthographic projection of the light emitting device (6) on the base substrate (1) may cover an orthographic projection of the via hole on the base substrate (1).
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公开(公告)号：US11074868B2
公开(公告)日：2021-07-27
申请号：US16823680
申请日：2020-03-19
Inventor： Zhidong Yuan , Yongqian Li , Can Yuan , Song Meng
IPC: G09G3/325 , G09G3/3291 , G09G3/3266
Abstract: Embodiments of the present disclosure provide a pixel circuit, a display panel, and a display device. The pixel circuit includes: a first transistor; a light emitting unit, a cathode being grounded; a second transistor; a third transistor; a fourth transistor; and a capacitor, a first terminal being coupled to the control electrode of the third transistor, and a second terminal being coupled to the second electrode of the third transistor.
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公开(公告)号：US12300168B2
公开(公告)日：2025-05-13
申请号：US18026827
申请日：2022-06-14
Inventor： Can Yuan , Yongqian Li , Zhidong Yuan
IPC: G09G3/3233 , H10K59/131
Abstract: Provided is a display panel. The display panel includes: a substrate; a plurality of first control lines and a plurality of second control lines on a side of the substrate; and a plurality of subpixels arranged in an array on the side of the substrate, wherein at least two of the plurality of subpixels share a first node; wherein the subpixel includes a first circuit and a second circuit, the first circuit and the second circuit being configured to control a voltage at the first node in response to a first control signal and a second control signal; wherein in the display panel, a sum of a number of the plurality of first control lines and a number of the plurality of second control lines is less than or equal to a number of the subpixels in a column direction.
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