Superconducting bump bonds
    21.
    发明授权

    公开(公告)号:US11133451B2

    公开(公告)日:2021-09-28

    申请号:US16557412

    申请日:2019-08-30

    Applicant: Google LLC

    Abstract: A device includes a first chip having a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, a superconducting bump bond on the barrier layer, and a second chip joined to the first chip by the superconducting bump bond, the second chip having a first quantum circuit element, in which the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element.

    INTEGRATED CIRCUIT DESIGN SYSTEM AND METHOD

    公开(公告)号:US20210294955A1

    公开(公告)日:2021-09-23

    申请号:US17340825

    申请日:2021-06-07

    Applicant: Google LLC

    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for parameterization of physical dimensions of discrete circuit components for component definitions that define discrete circuit components. The component definitions may be selected for use in a device design. When a parametrization of a particular version of a discrete circuit component definition is changed, the version level of the device design is also changed and the circuit layout for the device design is physically verified for the new version level.

    SIGNAL DISTRIBUTION FOR A QUANTUM COMPUTING SYSTEM

    公开(公告)号:US20210175095A1

    公开(公告)日:2021-06-10

    申请号:US17263619

    申请日:2018-07-30

    Applicant: Google LLC

    Abstract: A method of fabricating a carrier chip for distributing signals among circuit elements of a quantum computing device, includes: providing a multilayer wiring stack, the multilayer wiring stack comprising alternating layers of dielectric material and wiring; bonding a capping layer to the multilayer wiring stack, in which the capping layer includes a single crystal silicon dielectric layer; forming a via hole within the capping layer, in which the via hole extends to a first wiring layer of the multilayer wiring stack; forming an electrically conductive via within the via hole and electrically coupled to the first wiring layer; and forming a circuit element on a surface of the capping layer, in which the circuit element is directly electrically coupled to the electrically conductive via.

    Integrating circuit elements in a stacked quantum computing device

    公开(公告)号:US10950654B2

    公开(公告)日:2021-03-16

    申请号:US16487555

    申请日:2017-12-12

    Applicant: Google LLC

    Abstract: A stacked quantum computing device including: a first chip including a superconducting qubit, where the superconducting qubit includes a superconducting quantum interference device (SQUID) region, a control region, and a readout region, and a second chip bonded to the first chip, where the second chip includes a first control element overlapping with the SQUID region, a second control element displaced laterally from the control region and without overlapping the control region, and a readout device overlapping the readout region.

    INTEGRATING CIRCUIT ELEMENTS IN A STACKED QUANTUM COMPUTING DEVICE

    公开(公告)号:US20200058702A1

    公开(公告)日:2020-02-20

    申请号:US16487555

    申请日:2017-12-12

    Applicant: Google LLC

    Abstract: A stacked quantum computing device including: a first chip including a superconducting qubit, where the superconducting qubit includes a superconducting quantum interference device (SQUID) region, a control region, and a readout region, and a second chip bonded to the first chip, where the second chip includes a first control element overlapping with the SQUID region, a second control element displaced laterally from the control region and without overlapping the control region, and a readout device overlapping the readout region.

Patent Agency Ranking