公开(公告)号：US20210248451A1

公开(公告)日：2021-08-12

申请号：US16874894

申请日：2020-05-15

Applicant: Google LLC

Inventor： Gurushankar Rajamani ,  Alice Kuo

IPC: G06N3/063 ,  G06F3/06 ,  G06N3/04

Abstract: Methods, systems, and apparatus, including computer-readable media, are described for interleaving memory requests to accelerate memory accesses at a hardware circuit configured to implement a neural network model. A system generates multiple requests that are processed against a memory of the system. Each request is used to retrieve data from the memory. For each request, the system generates multiple sub-requests based on a respective size of the data to be retrieved using the request. The system generates a sequence of interleaved sub-requests that includes respective sub-requests of a first request interleaved among respective sub-requests of a second request. Based on the sequence of interleaved sub-requests, a module of the system receives respective portions of data accessed from different address locations of the memory. The system processes each of the respective portions of data to generate a neural network inference using the neural network model implemented at the hardware circuit.