公开(公告)号：US20100238753A1

公开(公告)日：2010-09-23

申请号：US12716363

申请日：2010-03-03

申请人： Yen-Huei CHEN ,  Cheng Hung LEE

发明人： Yen-Huei CHEN ,  Cheng Hung LEE

IPC分类号： G11C5/14

CPC分类号： G11C11/413 ,  G11C11/412

摘要： An integrated circuit includes at least one memory array for storing data. A first switch is coupled with the memory array. A first power line is coupled with the first switch. The first power line is operable to supply a first power voltage. A second switch is coupled with the memory array. A second power line is coupled with the second switch. The second power line is operable to supply a second power voltage for retaining the data during a retention mode. A third power line is coupled with the memory array. The third power line is capable of providing a third power voltage.

摘要翻译： 集成电路包括用于存储数据的至少一个存储器阵列。 第一开关与存储器阵列耦合。 第一电力线与第一开关耦合。 第一电力线可操作以提供第一电力电压。 第二开关与存储器阵列耦合。 第二电源线与第二开关耦合。 第二电源线可操作以在保持模式期间提供用于保留数据的第二电源电压。 第三电源线与存储器阵列耦合。 第三电源线能够提供第三电源电压。