公开(公告)号：US10101381B2

公开(公告)日：2018-10-16

申请号：US13600460

申请日：2012-08-31

申请人： Erkan Acar ,  Pooya Tadayon ,  Armen Y. Balian ,  Ethan Caughey

发明人： Erkan Acar ,  Pooya Tadayon ,  Armen Y. Balian ,  Ethan Caughey

IPC分类号： G01R31/26 ,  G01R3/00 ,  G01R31/28 ,  G01R1/073

摘要： A test system includes a test printed circuit board (PCB), a flip chip package mounted on the PCB, one or more test probes coupled to the flip chip package and a first integrated circuit (IC) coupled to the test probes to enable testing of the first IC using electrical circuitry of the flip chip package.

公开(公告)号：US20140062522A1

公开(公告)日：2014-03-06

申请号：US13600460

申请日：2012-08-31

申请人： Erkan Acar ,  Pooya Tadayon ,  Armen Y. Balian ,  Ethan Caughey

发明人： Erkan Acar ,  Pooya Tadayon ,  Armen Y. Balian ,  Ethan Caughey

IPC分类号： G01R31/26 ,  G01R3/00

CPC分类号： G01R31/2607 ,  G01R1/07378 ,  G01R3/00 ,  G01R31/2889 ,  Y10T29/49004 ,  Y10T29/49128

摘要： A test system includes a test printed circuit board (PCB), a flip chip package mounted on the PCB, one or more test probes coupled to the flip chip package and a first integrated circuit (IC) coupled to the test probes to enable testing of the first IC using electrical circuitry of the flip chip package.

摘要翻译： 测试系统包括测试印刷电路板（PCB），安装在PCB上的倒装芯片封装，耦合到倒装芯片封装的一个或多个测试探针和耦合到测试探针的第一集成电路（IC），以测试 第一个IC使用倒装芯片封装的电路。

公开(公告)号：US20100151598A1

公开(公告)日：2010-06-17

申请号：US12333842

申请日：2008-12-12

申请人： Eric J. M. Moret ,  Pooya Tadayon

发明人： Eric J. M. Moret ,  Pooya Tadayon

IPC分类号： H01L21/66 ,  H01L23/34

CPC分类号： H01L22/20 ,  G01R31/2831 ,  G01R31/2886 ,  H01L22/14 ,  H01L2924/014

摘要： In some embodiments, a temporary package for at-speed functional test of semiconductor chip, including high power chips, is presented. In this regard, a method is introduced including placing an integrated circuit die on a contactor layer, the contactor layer to electrically couple contacts on the integrated circuit die with contacts on a multi-layer substrate designed to be permanently attached with the integrated circuit die, placing an integrated heat spreader over the integrated circuit die, and bonding the integrated heat spreader with the substrate, the integrated heat spreader holding the integrated circuit die in place to form a temporary package. Other embodiments are also disclosed and claimed.

摘要翻译： 在一些实施例中，提供了用于包括高功率芯片的半导体芯片的高速功能测试的临时封装。 在这方面，引入了将集成电路管芯放置在接触器层上的方法，接触器层将集成电路管芯上的触点与设计成永久地与集成电路管芯连接的多层基板上的触点电耦合， 将集成散热器放置在集成电路管芯上，并将集成散热器与基板接合，将集成散热器固定在一起形成临时封装。 还公开并要求保护其他实施例。

公开(公告)号：US06627978B2

公开(公告)日：2003-09-30

申请号：US09967748

申请日：2001-09-28

申请人： Prateek Dujari ,  Franklin Monzon ,  Pooya Tadayon

发明人： Prateek Dujari ,  Franklin Monzon ,  Pooya Tadayon

IPC分类号： H01L23495

CPC分类号： H01L23/49833 ,  H01L23/481 ,  H01L23/49816 ,  H01L2224/1718 ,  H01L2224/73204

摘要： A device and method for increasing input/output from a die by making electrically conductive microvias connecting the integrated circuit with a backside of the die. The backside electrically conductive microvias connect an integrated circuit in the die to pads on the backside of the die. A superstrate is situated on top of the die and connects to the microvias using controlled collapse chip connections (C4) with a thermal interface material (TIM) surrounding the electrical connections. A superstrate lead system electrically connects the backside pads to wirebonds that connect with either the substrate or directly to the motherboard. Heat dissipates from the die via the TIM to the superstrate to a heat sink situated on top of the superstate.