公开(公告)号：US08316193B2

公开(公告)日：2012-11-20

申请号：US12629682

申请日：2009-12-02

Applicant: Ross Charles Knippel ,  Jeffrey W. Sheldon ,  Ole Agesen

Inventor： Ross Charles Knippel ,  Jeffrey W. Sheldon ,  Ole Agesen

IPC: G06F12/00

CPC classification number: G06F9/45516 ,  G06F9/45558 ,  G06F2009/45583

Abstract: A mechanism for a binary translator to emit code that will pre-generate information about a memory segment when a segment selector is assigned to a segment register. The binary translator emits code that will be executed when a memory access using that segment register is encountered and the emitted code will access the pre-generated information when evaluating the memory access request. Memory accesses, where a number of bytes being accessed is less than or equal to a predetermined value, are validated with a number of steps in the code emitted by the binary translator.

Abstract translation: 一种二进制转换器发出代码的机制，当段选择器被分配给段寄存器时，该代码将预先生成关于存储器段的信息。 二进制翻译器发出将在遇到使用该段寄存器的存储器访问时执行的代码，并且当评估存储器访问请求时，发出的代码将访问预生成的信息。 存储器访问（其中访问的字节数小于或等于预定值）通过二进制翻译器发出的代码中的多个步骤来验证。