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公开(公告)号：US20250056835A1
公开(公告)日：2025-02-13
申请号：US18932782
申请日：2024-10-31
Inventor： Cheng-Bo SHU , Yun-Chi WU
IPC: H01L29/78 , H01L21/8234 , H01L27/088 , H01L29/40 , H01L29/66
Abstract: An integrated circuit structure includes a semiconductor substrate, first and second source/drain features, a gate dielectric layer, a gate electrode, a field plate electrode, first and second metal silicide layers, a dielectric layer, and a spacer. The gate electrode and the field plate electrode are over the gate dielectric layer and respectively vertically overlapping a well region and a drift region in the semiconductor substrate. A first sidewall of the field plate electrode faces the gate electrode. The first and second metal silicide layers are over the gate electrode and the field plate electrode, respectively. The dielectric layer has a first portion between the gate electrode and the first sidewall of the field plate electrode and a second portion below a bottom surface of the field plate electrode. The spacer is alongside a second sidewall of the field plate electrode and over the second portion of the dielectric layer.
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12.发明申请
公开(公告)号：US20250048710A1
公开(公告)日：2025-02-06
申请号：US18411675
申请日：2024-01-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Lo-Heng CHANG , Huan-Chieh SU , Chun-Yuan CHEN , Kuo-Cheng CHIANG , Chih-Hao WANG
IPC: H01L29/417 , H01L21/762 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
Abstract: An integrated circuit includes a substrate having a semiconductor layer. The integrated circuit includes a transistor. The transistor includes stacked channels above the semiconductor layer, a first source/drain region in contact with the channels, and a second source/drain region in contact with the channels. A backside source/drain contact is positioned in the substrate directly below and electrically coupled to the first source/drain region. A frontside source/drain contact is directly above and electrically coupled to the first source/drain region. A bottom semiconductor structure is positioned below the second source/drain region and in contact with the semiconductor layer.
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公开(公告)号：US20250048681A1
公开(公告)日：2025-02-06
申请号：US18661851
申请日：2024-05-13
Applicant: Kennametal Inc.
Inventor： Tim Guter , Jürgen Schwägerl
IPC: H01L29/78 , H01L21/467 , H01L29/08 , H01L29/24 , H01L29/40 , H01L29/417 , H01L29/51 , H01L29/66
Abstract: A method for producing a cutting tool, in particular a drill bit, is specified wherein the cutting tool has a front end (F) at the front and a rear end (R) toward the rear, wherein a tool tip is formed on the front end (F), a point thinning is ground at the tool tip with a grinding tool, the point thinning being ground to be narrower toward the front than toward the rear. The point thinning is ground with a constant point thinning angle (AW). Furthermore, a corresponding cutting tool is specified.
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公开(公告)号：US20250046718A1
公开(公告)日：2025-02-06
申请号：US18524661
申请日：2023-11-30
Inventor： Chun-Yuan CHEN , Huan-Chieh SU , Kuo-Cheng CHIANG , Chih-Hao WANG
IPC: H01L23/535 , H01L21/768 , H01L29/06 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775
Abstract: Embodiments of the present disclosure provide a method for forming backside gate contacts and semiconductor fabricated thereof. A semiconductor device includes both signal outputs, such as source/drain contacts, and signal inputs, such as gate contacts, formed on a backside of the substrate. The backside gate contacts and backside source/drain contacts are formed in a self-aligned manner.
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公开(公告)号：US12218123B2
公开(公告)日：2025-02-04
申请号：US17948929
申请日：2022-09-20
Applicant: ROHM CO., LTD.
Inventor： Keisuke Fukae
Abstract: The present disclosure provides a chip part. The chip part includes a substrate, a first external electrode, a second external electrode, a capacitor portion, a lower electrode, a capacitive film and an upper electrode. The first external electrode and the second external electrode are disposed on a first main surface of the substrate. The capacitor portion is disposed on the first main surface of the substrate. The lower electrode includes a first body portion and a first peripheral portion integrally drawn out around the capacitor portion from the first body portion. The capacitive film includes a second body portion disposed within the capacitor portion and a second peripheral portion integrally drawn out from the second body portion to the first peripheral portion. The upper electrode is disposed on the capacitive film.
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公开(公告)号：US20250040222A1
公开(公告)日：2025-01-30
申请号：US18772473
申请日：2024-07-15
Applicant: Renesas Electronics Corporation
Inventor： Yu NAGAHAMA
IPC: H01L29/40 , H01L21/28 , H01L21/311 , H01L29/423
Abstract: The reliability of the semiconductor device is improved. A field plate electrode FP is formed inside the trench TR via an insulating film IF1. The other part of the field plate electrode FP is selectively retracted toward the bottom of the trench TR so that a part of the field plate electrode FP remains as a lead-out part FPa. A silicon oxide film OX1 is formed on the upper surface of the field plate electrode FP by thermal oxidation. The insulating film IF1 located on the upper surface TS of the semiconductor substrate SUB and the silicon oxide film OX1 are removed, and the insulating film IF1 is retracted so that its upper surface position is lower than the upper surface position of the field plate electrode FP.
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公开(公告)号：US20250040220A1
公开(公告)日：2025-01-30
申请号：US18226764
申请日：2023-07-26
Inventor： Chen-Dong Tzou , Wei-Chih Cheng , Chia-Hao Lee
IPC: H01L29/40 , H01L29/20 , H01L29/66 , H01L29/778
Abstract: A high electron mobility transistor includes a semiconductor channel layer and a semiconductor barrier layer disposed on a substrate in sequence. A source electrode and a drain electrode are disposed on the semiconductor channel layer. A semiconductor cap layer is disposed on the semiconductor barrier layer. A first dielectric layer is disposed over the source electrode, the semiconductor cap layer and the drain electrode. A first via passes through the first dielectric layer and is extended downward onto the semiconductor cap layer. A gate electrode is disposed on the first dielectric layer and in contact with the first via. A first field plate is disposed in the first dielectric layer. A second field plate is disposed on the first dielectric layer and in contact with the first field plate.
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公开(公告)号：US20250038000A1
公开(公告)日：2025-01-30
申请号：US18227286
申请日：2023-07-27
Applicant: Applied Materials, Inc.
Inventor： Qintao ZHANG , Ludovico MEGALINI , Wei ZOU , Hans-Joachim L. GOSSMANN , William O. CHARLES
IPC: H01L21/04 , H01L21/266 , H01L21/306 , H01L29/40
Abstract: Disclosed herein are methods for forming MOSFET trenches with improved corner properties. In some embodiments, a method may include providing a device structure including an epitaxial layer and a hard mask over the epitaxial layer, and forming a trench through the well and the epitaxial layer, wherein the trench is defined by a sidewall, a bottom, and a corner at an intersection of the sidewall and the bottom. The method may further include implanting the device structure by delivering ions into the corner and into the bottom of the trench, and etching the trench to increase rounding of the corner.
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公开(公告)号：US12211912B2
公开(公告)日：2025-01-28
申请号：US16968877
申请日：2020-06-30
Applicant: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
Inventor： Hao Li , Anbang Zhang , Jian Wang , Haoning Zheng
IPC: H01L29/423 , H01L29/20 , H01L29/40 , H01L29/417 , H01L29/66 , H01L29/778
Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a III-nitride layer, a gate, a connection structure, and a gate bus. The gate is disposed over the III-nitride layer. The connection structure is disposed over the gate. The gate bus extends substantially in parallel to the gate and disposed over the connection structure from a top view perspective. The gate bus is electrically connected to the gate through the connection structure.
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公开(公告)号：US12211807B2
公开(公告)日：2025-01-28
申请号：US18490866
申请日：2023-10-20
Applicant: Texas Instruments Incorporated
Inventor： Alexei Sadovnikov , Sheldon Douglas Haynie , Ujwal Radhakrishna
Abstract: A microelectronic device includes a doped region of semiconductor material having a first region and an opposite second region. The microelectronic device is configured to provide a first operational potential at the first region and to provide a second operational potential at the second region. The microelectronic device includes field plate segments in trenches extending into the doped region. Each field plate segment is separated from the semiconductor material by a trench liner of dielectric material. The microelectronic device further includes circuitry electrically connected to each of the field plate segments. The circuitry is configured to apply bias potentials to the field plate segments. The bias potentials are monotonic with respect to distances of the field plate segments from the first region of the doped region.
