公开(公告)号：US20240373614A1

公开(公告)日：2024-11-07

申请号：US18771937

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Chih-Chuan Yang ,  Hsin-Wen Su ,  Kian-Long Lim ,  Chien-Chih Lin

IPC: H10B10/00 ,  G11C11/412 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66

Abstract: An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.

公开(公告)号：US20240371412A1

公开(公告)日：2024-11-07

申请号：US18453634

申请日：2023-08-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hidehiro Fujiwara ,  Chih-Yu Lin ,  Yuichiro Ishii ,  Makoto Yabuuchi ,  Masaya Hamada ,  Koji Nii ,  Yen-Huei Chen

IPC: G11C5/06 ,  G11C11/412 ,  H10B10/00

Abstract: A semiconductor device includes a first memory cell in a 4CPP architecture; a second memory cell formed in the 4CPP architecture and physically disposed next to the first memory cell along a first lateral direction; a first word line extending along the first lateral direction and operatively coupled to the first memory cell; a second word line extending along the first lateral direction and operatively coupled to the first memory cell; a third word line extending along the first lateral direction and operatively coupled to the second memory cell; a fourth word line extending along the first lateral direction and operatively coupled to the second memory cell; a first bit line extending along a second lateral direction perpendicular to the first lateral direction and operatively coupled to the first memory cell; and a second bit line extending along the second lateral direction and operatively coupled to the second memory cell.

公开(公告)号：US20240341074A1

公开(公告)日：2024-10-10

申请号：US18749271

申请日：2024-06-20

Applicant: Socionext Inc.

Inventor： Masanobu HIROSE ,  Yasunori MURASE

IPC: H10B10/00 ,  G11C11/412 ,  G11C11/419

CPC classification number: H10B10/12 ,  G11C11/412 ,  G11C11/419 ,  H10B10/18

Abstract: Nanosheets 21 to 23 are formed in line in this order in the X direction, and nanosheets 24 to 26 are formed in line in this order in the X direction. In a buried interconnect layer, a power line 11 is formed between the nanosheets 22 and 25 as viewed in plan. A face of the nanosheet 22 on a first side as one of the sides in the X direction is exposed from a gate interconnect 32. A face of the nanosheet 25 on a second side as the other side in the X direction is exposed from a gate interconnect 35.

公开(公告)号：US20240341073A1

公开(公告)日：2024-10-10

申请号：US18748475

申请日：2024-06-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chuan YANG ,  Kuo-Hsiu HSU ,  Chia-Hao PAO ,  Shih-Hao LIN

IPC: H10B10/00 ,  G11C11/412 ,  G11C11/417 ,  H01L27/092

CPC classification number: H10B10/12 ,  G11C11/412 ,  G11C11/417 ,  H01L27/092

Abstract: A four times contacted poly pitch (4CPP) static random-access memory (SRAM) cell layout is disclosed that forms six SRAM transistors from one OD region and four poly lines at a frontside of a substrate and provides a double-sided routing structure for word lines, bit lines, and/or voltage lines. For example, a vertical SRAM is disclosed that stacks transistors, vertically, to facilitate scaling needed for advanced IC technology nodes and improve memory performance. The vertical SRAM further includes a double-sided routing structure, which facilitates placement of bit lines, word lines, and voltage lines in a backside metal one (M1) layer and/or a frontside M1 layer to minimize line capacitance and line resistance.

公开(公告)号：US12114473B2

公开(公告)日：2024-10-08

申请号：US17828123

申请日：2022-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jhon-Jhy Liaw

IPC: G11C7/12 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  H10B10/00 ,  G11C8/08 ,  G11C8/16

CPC classification number: H10B10/18 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C7/12 ,  G11C8/08 ,  G11C8/16

Abstract: Semiconductor devices are provided. A write port circuit is configured to perform a write function according to the write word line and the first and second write bit lines. The first read port circuit is configured to perform first read function according to the first read bit line and the first read word line. The second read port circuit is configured to perform second read function according to the second read bit line and the second read word line. The transistors of the first and second read port circuits share a first active structure extending in the first direction. The first read bit line and the second read bit line extend in the first direction in a first metallization layer, and the first write bit line and the second write bit line extend in the first direction in a second metallization layer over the first metallization layer.

公开(公告)号：US20240331765A1

公开(公告)日：2024-10-03

申请号：US18741051

申请日：2024-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Wei Wang ,  Chia-Hao Pao ,  Choh Fei Yeap ,  Yu-Kuan Lin ,  Kian-Long Lim

IPC: G11C11/412 ,  G11C11/419 ,  H10B10/00

CPC classification number: G11C11/412 ,  G11C11/419 ,  H10B10/12

Abstract: Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.

公开(公告)号：US12106801B2

公开(公告)日：2024-10-01

申请号：US17858376

申请日：2022-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhon Jhy Liaw

IPC: G11C11/412 ,  G11C11/419 ,  G11C5/02 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C5/025 ,  G11C7/1096 ,  G11C7/12

Abstract: An array of memory cells is arranged into a plurality of columns and rows. A first signal line extends through a first column of the plurality of columns. The first signal line is electrically coupled to the memory cells in the first column. A first end portion of the first signal line is configured to receive a logic high signal from a first circuit during a first operational state of the memory device and a logic low signal from the first circuit during a second operational state of the memory device. A second circuit includes a plurality of transistors. The transistors are configured to be turned on or off to electrically couple a second end portion of the first signal line to a logic low source when the first end portion of the first signal line is configured to receive the logic low signal from the first circuit.

公开(公告)号：US12101921B2

公开(公告)日：2024-09-24

申请号：US17871764

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Chih-Chuan Yang ,  Hsin-Wen Su ,  Kian-Long Lim ,  Chien-Chih Lin

IPC: H10B10/00 ,  G11C11/412 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66

CPC classification number: H10B10/12 ,  G11C11/412 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/6656

Abstract: An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.

公开(公告)号：US12089391B2

公开(公告)日：2024-09-10

申请号：US17853098

申请日：2022-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jhon-Jhy Liaw

IPC: G11C11/412 ,  G11C7/12 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4097 ,  H10B10/00

CPC classification number: H10B10/12 ,  G11C7/12 ,  G11C11/4085 ,  G11C11/4096 ,  G11C11/4097 ,  H10B10/18

Abstract: Semiconductor devices are provided. A memory cell includes a first pull-down transistor, a second pull-down transistor, a first pass-gate transistor, and a second pass-gate transistor formed over a P-type well region, and a first pull-up transistor, a second pull-up transistor, a first isolation transistor, and a second isolation transistor formed over an N-type well region. The first and second pull-down transistors and the first and second pass-gate transistors share a first active region. The first and second pull-up transistors and the first and second isolation transistors share a second active region. The gates of the first and second isolation transistors are electrically connected to a VDD line. The gates of the first and second pass-gate transistors are electrically connected to a WL landing pad. The sources of the first and second pass-gate transistors are electrically connected to the first bit line and the second bit line, respectively.

公开(公告)号：US20240296883A1

公开(公告)日：2024-09-05

申请号：US18418060

申请日：2024-01-19

Applicant: FlashSilicon Incorporation

Inventor： LEE WANG

IPC: G11C11/419 ,  G11C11/412 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C11/418

Abstract: A memory device is disclosed, comprising a 4T-SRAM cell and a read circuit. The 4T-SRAM cell comprising two P-type MOSFET devices for a data bit storage and two N-type MOSFET for accessing switches has benefits of less numbers of MOSFET devices for smaller cell size and low leakage current than the conventional 6T-SRAM cell. The read circuit comprises a latch and a discharge device. The latch with two output nodes is coupled between a supply voltage rail and a ground voltage rail. The discharge device is coupled to the two output nodes, a bit line pair and the ground voltage rail. Since one of two storage nodes for the 4T-SRAM cell is floating, the stored data in the 4T-SRAM cell is vulnerable for conventional read operations. The read circuit of the invention resolves the vulnerability issue of the 4T-SRAM cell.