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11.发明公开公开(公告)号：US20240045619A1
公开(公告)日：2024-02-08
申请号：US18484563
申请日：2023-10-11
Applicant: KIOXIA CORPORATION
Inventor： Shinichi KANNO
CPC classification number: G06F3/0659 , G06F3/0616 , G06F3/0679 , G06F3/0604 , G06F3/0608 , G06F3/0631 , G06F3/0652 , G06F3/0688 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3495
Abstract: According to one embodiment, a storage system performs a first allocation operation of allocating, for a first namespace, a plurality of first blocks included in the blocks of a nonvolatile memory. The storage system performs a read operation, a write operation or an erase operation on one of the first blocks in response to a command received from a host to read, write or erase the one first block, counts the total number of erase operations performed on the first blocks, and notifies the host of the counted number of erase operations in response to a command received from the host to obtain an erase count associated with the first namespace.
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公开(公告)号：US11886710B2
公开(公告)日：2024-01-30
申请号：US17552060
申请日：2021-12-15
Applicant: Micron Technology, Inc.
Inventor： Paolo Amato , Daniele Balluchi , Danilo Caraccio , Emanuele Confalonieri , Marco Dallabora
IPC: G06F11/00 , G06F3/06 , G06F11/10 , G11C16/34 , G06F12/1009
CPC classification number: G06F3/0611 , G06F3/0616 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G06F3/0683 , G06F11/1048 , G06F11/1076 , G06F12/1009 , G11C16/3495 , G06F3/0619 , G06F3/0634 , G06F2212/65
Abstract: The present disclosure includes apparatuses and methods related to memory operations on data. An example method can include executing an operation by writing a first managed unit to a second managed unit, and placing the first managed unit in a free state, wherein the first managed unit is located at a particular distance from the second managed unit.
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公开(公告)号：US20240021252A1
公开(公告)日：2024-01-18
申请号：US18365929
申请日：2023-08-04
Applicant: Kioxia Corporation
Inventor： Yoshihisa KOJIMA
CPC classification number: G11C16/32 , G11C16/26 , G11C16/08 , G11C11/5628 , G11C16/3495 , G11C16/0483 , G11C7/04 , G11C16/10 , G11C2211/5648
Abstract: A memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. The memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.
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公开(公告)号：US11869596B2
公开(公告)日：2024-01-09
申请号：US18117520
申请日：2023-03-06
Applicant: Kioxia Corporation
Inventor： Suguru Nishikawa , Yoshihisa Kojima , Riki Suzuki , Masanobu Shirakawa , Toshikatsu Hida
IPC: G06F12/00 , G11C16/10 , G11C16/04 , G11C16/14 , G06F3/06 , G11C11/56 , G11C16/08 , G11C16/34 , G11C29/02 , G11C29/42 , G11C16/32 , H10B43/27 , H10B43/35
CPC classification number: G11C16/10 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/08 , G11C16/14 , G11C16/32 , G11C16/349 , G11C16/3459 , G11C16/3495 , G11C29/021 , G11C29/028 , G11C29/42 , G11C11/5671 , H10B43/27 , H10B43/35
Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.
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公开(公告)号：US11854634B2
公开(公告)日：2023-12-26
申请号：US17007499
申请日：2020-08-31
Applicant: Micron Technology, Inc.
Inventor： Aswin Thiruvengadam , Daniel L Lowrance , Peter Feeley
IPC: G11C29/02 , G11C16/10 , G11C16/32 , G11C16/34 , G06F12/02 , G06F3/06 , G11C7/10 , G06F16/18 , G11C7/04 , G11C29/44
CPC classification number: G11C29/028 , G06F3/0652 , G06F12/0246 , G06F12/0292 , G06F16/1847 , G11C7/1072 , G11C16/10 , G11C16/32 , G11C16/3495 , G06F2212/7209 , G11C7/04 , G11C2029/4402
Abstract: The present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. An example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number of sets of trim settings based on desired operational characteristics for the array of memory cells.
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公开(公告)号：US11837298B2
公开(公告)日：2023-12-05
申请号：US17903390
申请日：2022-09-06
Applicant: Innogrit Technologies Co., Ltd.
CPC classification number: G11C16/3495 , G06F12/0253 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/349
Abstract: Systems, apparatus and methods are provided for performing program operations in a non-volatile storage system. In one embodiment, there is provided a method that may comprise categorizing active storage blocks of a non-volatile storage device into a robust group and a less-robust group based on a number of factors including page error count, program time and number of Program/Erase (P/E) cycles; determining that a cache program operation needs to be performed; selecting a first storage block from the robust group to perform the cache program operation; determining that a regular program operation needs to be performed; and selecting a second storage block from the less-robust group to perform the regular program operation.
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公开(公告)号：US11776638B2
公开(公告)日：2023-10-03
申请号：US18149373
申请日：2023-01-03
Applicant: KIOXIA CORPORATION
Inventor： Yoshihisa Kojima
CPC classification number: G11C16/32 , G11C7/04 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3495 , G11C2211/5648
Abstract: A memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. The memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.
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18.发明公开
公开(公告)号：US20230282295A1
公开(公告)日：2023-09-07
申请号：US17685113
申请日：2022-03-02
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Xue Bai Pitner , Ken Oowada
CPC classification number: G11C16/3495 , G11C16/102 , G11C16/26 , G11C16/08 , G11C16/0433
Abstract: A method for programming a target memory cell of a memory array of a non-volatile memory system, the method comprises determining a total number of erase/programming (EP) cycles that were applied previously to the memory cell and, (1) if the determined total number of cycles does not exceed a threshold value, applying an asymmetric programming scheme, and, (2) if the determined total number of cycles exceeds the threshold value, applying a symmetric programming scheme. Further, a magnitude of a boosting voltage bias (VPASS) that is to be applied to an unselected word line may be determined according to the determined total number of erase/programming (EP) cycles.
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公开(公告)号：US11735273B2
公开(公告)日：2023-08-22
申请号：US17580561
申请日：2022-01-20
Applicant: Western Digital Technologies, Inc.
Inventor： Mohsen Purahmad , Chao-Han Cheng , Dongxiang Liao , Bo Lei
CPC classification number: G11C16/26 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/3495 , G11C29/52 , G11C11/5621 , G11C11/5671 , G11C16/0483
Abstract: Apparatus and methods for recovery after an abort event are described. A data storage system may comprise a non-volatile memory device, having one or more wordlines configured to receive a read level voltage, and a controller. The controller is configured to detect whether a write abort event occurred for the data storage system. The controller is configured to determine a first voltage offset based on one or more of a wear-level indication of the non-volatile memory device, or one or more voltage parameters of the non-volatile memory device. The controller is configured to determine, based on the first voltage offset, an adjusted read level voltage. The controller is configured to apply the adjusted read level voltage to a wordline of the non-volatile memory device. The controller is configured to read data, based on the applied adjusted read level voltage, from the wordline of the non-volatile memory device.
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公开(公告)号：US11727998B2
公开(公告)日：2023-08-15
申请号：US17512394
申请日：2021-10-27
Applicant: KIOXIA CORPORATION
Inventor： Shigehiro Asano , Neil Buxton , Julien Margetts , Shunichi Igahara , Takehiko Amaki
CPC classification number: G11C16/3431 , G11C8/12 , G11C16/26 , G11C16/3495 , G11C16/0483
Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.
