公开(公告)号：US11711081B2

公开(公告)日：2023-07-25

申请号：US17511833

申请日：2021-10-27

Applicant: XILINX, INC.

Inventor： Roswald Francis

IPC: H03K5/01 ,  H03K19/0185 ,  H03K19/17788 ,  H03K19/17736 ,  H03K19/00

CPC classification number: H03K19/01855 ,  H03K19/0016 ,  H03K19/1774 ,  H03K19/17788

Abstract: Techniques and apparatus for reducing low frequency power supply spurs in clock signals in a clock distribution network. One example circuit for clock distribution generally includes a plurality of logic inverters coupled in series and configured to drive a clock signal and a current-starved inverter coupled in parallel (or in series) with a logic inverter in the plurality of logic inverters.