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公开(公告)号：US11127642B2
公开(公告)日：2021-09-21
申请号：US16349984
申请日：2018-11-20
Inventor： Xue Li
IPC: H01L21/66 , H01L23/60 , H01L27/32 , G01R31/317 , G01R31/28
Abstract: A test circuit layout structure for a display panel is disclosed and includes a chip on film (COF) bonding region having two ends connected to two power conductor regions extending toward an active area; a test circuit region located between the COF bonding region and the two power conductor regions; two test pad regions and two electrostatic protection regions are both distributed around two sides of the COF bonding region; wherein a plurality of wires extend from the test pad regions and are configured to couple the electrostatic protection regions, the COF bonding region, and the test circuit region; wherein resistivity of the wires and resistivity of the power conductor regions are the same; and wherein the wires bypass the power conductor regions disposed in the same layer as the wires, alternatively, the wires and the power conductor regions are overlapped in an insulation manner.
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公开(公告)号：US10818693B2
公开(公告)日：2020-10-27
申请号：US15751012
申请日：2018-01-23
IPC: H01L27/12 , H01L23/498
Abstract: The present invention provides an array substrate comprising a substrate, an inorganic layer formed on the substrate, a metal wiring formed on the inorganic layer, and an organic layer on the inorganic layer and covering the metal wiring; wherein the metal wiring and/or the inorganic layer include a bending performance enhancement structure. In this invention, by means of providing the bending performance enhancement structure in the metal wiring and/or the inorganic layer, the stress in the bending region is released when the flexible display is bent, so as to prevent the bending region from fracture or damage and improve the bending performance.
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