公开(公告)号：US12237395B2

公开(公告)日：2025-02-25

申请号：US17676216

申请日：2022-02-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Wei Lin ,  Chun-Chieh Chiu ,  Chun-Ling Lin ,  Shu Min Huang ,  Hsin-Fu Huang

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/768 ,  H01L29/20 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.

公开(公告)号：US09966425B1

公开(公告)日：2018-05-08

申请号：US15445953

申请日：2017-02-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jen-Po Huang ,  Chin-Fu Lin ,  Bin-Siang Tsai ,  Xu Yang Shen ,  Seng Wah Liau ,  Yen-Chen Chen ,  Ko-Wei Lin ,  Chun-Ling Lin ,  Kuo-Chih Lai ,  Ai-Sen Liu ,  Chun-Yuan Wu ,  Yang-Ju Lu

IPC: H01L21/8242 ,  H01L49/02

CPC classification number: H01L28/56 ,  H01L28/60

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.

公开(公告)号：US09685316B2

公开(公告)日：2017-06-20

申请号：US13775273

申请日：2013-02-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia Chang Hsu ,  Kuo-Chih Lai ,  Chun-Ling Lin ,  Bor-Shyang Liao ,  Pin-Hong Chen ,  Shu Min Huang ,  Min-Chung Cheng ,  Chi-Mao Hsu

IPC: H01L21/302 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  H01L21/67 ,  H01L21/3065 ,  H01L21/285

CPC classification number: H01L21/02063 ,  H01L21/28518 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/6708 ,  H01L21/67109 ,  H01L21/76804 ,  H01L21/76814

Abstract: A semiconductor process includes the following steps. A wafer on a pedestal is provided. The pedestal is lifted to approach a heating source and an etching process is performed on the wafer. An annealing process is performed on the wafer by the heating source. In another way, a wafer on a pedestal, and a heating source on a same side of the wafer as the pedestal are provided. An etching process is performed on the wafer by setting the temperature difference between the heating source and the pedestal larger than 180° C.

公开(公告)号：US09412653B2

公开(公告)日：2016-08-09

申请号：US14817227

申请日：2015-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Jia Chen ,  Chi-Mao Hsu ,  Tsun-Min Cheng ,  Chun-Ling Lin ,  Huei-Ru Tsai ,  Ching-Wei Hsu ,  Chin-Fu Lin ,  Hsin-Yu Chen

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76847 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.

Abstract translation: 硅通孔结构位于衬底的凹槽中。 贯通硅通孔结构包括阻挡层，缓冲层和导电层。 阻挡层覆盖凹部的表面。 缓冲层覆盖阻挡层。 导电层位于缓冲层上并填充凹槽，其中导电层和缓冲层之间的接触表面比缓冲层和阻挡层之间的接触表面更平滑。 此外，还提供了形成所述贯穿硅通孔结构的通硅通孔工艺。

公开(公告)号：US20240332189A1

公开(公告)日：2024-10-03

申请号：US18136885

申请日：2023-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Ko-Wei Lin ,  Ying-Wei Yen ,  Chun-Ling Lin ,  Po-Jen Chuang

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53266

Abstract: A method for fabricating an interconnect structure is disclosed. A substrate with a first dielectric layer is provided. A first conductor is formed in the first dielectric layer. A second dielectric layer is formed on the first dielectric layer. A trench is formed in the second dielectric layer to expose the top surface of the first conductor. An annealing process is performed on the top surface of the first conductor. The annealing process includes the conditions of a temperature of 400-450° C., duration less than 5 minutes, and gaseous atmosphere comprising hydrogen and nitrogen.

公开(公告)号：US10446489B2

公开(公告)日：2019-10-15

申请号：US16170059

申请日：2018-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Wei Lin ,  Hung-Miao Lin ,  Chun-Ling Lin ,  Ying-Lien Chen ,  Huei-Ru Tsai ,  Sheng-Yi Su

IPC: H01L23/528 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.

公开(公告)号：US10323332B2

公开(公告)日：2019-06-18

申请号：US15206321

申请日：2016-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ling Lin ,  Yen-Liang Lu ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chun-Hung Chen ,  Tsun-Min Cheng ,  Chi-Ray Tsai

IPC: C25D7/12 ,  C25D5/00 ,  C25D3/38 ,  C25D5/10 ,  C25D5/54 ,  H01L21/288 ,  H01L21/768

Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.

公开(公告)号：US20160319450A1

公开(公告)日：2016-11-03

申请号：US15206321

申请日：2016-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ling Lin ,  Yen-Liang Lu ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chun-Hung Chen ,  Tsun-Min Cheng ,  Chi-Ray Tsai

IPC: C25D5/54 ,  H01L21/768 ,  C25D7/12 ,  H01L21/288 ,  C25D3/38 ,  C25D5/10

CPC classification number: C25D5/54 ,  C25D3/38 ,  C25D5/00 ,  C25D5/10 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76879

Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.

Abstract translation: 提供电化学镀工艺。 半导体结构设置在电镀平台中。 进行预电镀步骤，其中预电镀步骤在固定电压环境下进行，并且在电流高于电镀平台的阈值电流之后持续0.2至0.5秒。 在预电镀步骤之后，对半导体结构进行第一电镀步骤。