公开(公告)号：US20150123210A1

公开(公告)日：2015-05-07

申请号：US14070596

申请日：2013-11-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-I Liao ,  Chun-Yu Chen

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/16 ,  H01L29/66795

Abstract: An epitaxial structure for a non-planar transistor is provided. A substrate has a fin-shaped structure. A gate is disposed across the fin-shaped structure. A silicon germanium epitaxial structure is disposed on the fin-shaped structure beside the gate, wherein the silicon germanium epitaxial structure has 4 surfaces and its aspect ratio of width and thickness is at a range of 1:1˜1.3. A method for forming said epitaxial structure is also provided.

Abstract translation: 提供了一种用于非平面晶体管的外延结构。 衬底具有鳍状结构。 门跨越鳍状结构设置。 在栅极旁边的鳍状结构上设置硅锗外延结构，其中硅锗外延结构具有4 <1,1,1“表面，其宽度和厚度的纵横比在1：1〜 1.3。 还提供了一种用于形成所述外延结构的方法。

公开(公告)号：US20220189770A1

公开(公告)日：2022-06-16

申请号：US17147477

申请日：2021-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Wei Su ,  Hao-Che Feng ,  Hsuan-Tai Hsu ,  Chun-Yu Chen ,  Wei-Hao Huang ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/762

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a fin-shaped structure on a substrate, forming a dielectric layer surrounding the fin-shaped structure, performing an anneal process to transform the dielectric layer into a shallow trench isolation (STI), removing the fin-shaped structure to form a trench, and forming a stack structure in the trench. Preferably, the stack structure includes a first semiconductor layer on the fin-shaped structure and a second semiconductor layer on the first semiconductor layer and the first semiconductor layer and the second semiconductor layer include different materials.

公开(公告)号：US09899498B2

公开(公告)日：2018-02-20

申请号：US15590510

申请日：2017-05-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Chen Chan ,  Yi-Fan Li ,  Yen-Hsing Chen ,  Chun-Yu Chen ,  Chung-Ting Huang ,  Zih-Hsuan Huang ,  Ming-Hua Chang ,  Yu-Shu Lin ,  Shu-Yen Chan

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (SiGe) layer epitaxially grown on the top surface and the lateral sidewalls of the fin; and a gate stack formed on the isolation layer and across the fin, wherein the fin and the gate stack respectively extend along a first direction and a second direction. The SiGe layer formed on the top surface has a first thickness, the SiGe layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30.

公开(公告)号：US20220069127A1

公开(公告)日：2022-03-03

申请号：US17033897

申请日：2020-09-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yu Chen ,  Bo-Lin Huang ,  Jhong-Yi Huang ,  Keng-Jen Lin ,  Yu-Shu Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/16

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.

公开(公告)号：US20190326414A1

公开(公告)日：2019-10-24

申请号：US16503461

申请日：2019-07-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Hsing Chen ,  Chun-Yu Chen ,  Chung-Ting Huang ,  Zih-Hsuan Huang ,  Yu-Chien Sung

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/033 ,  H01L21/3213 ,  H01L29/06

Abstract: A method for fabricating a semiconductor device is disclosed. A fin is formed on a substrate. The fin protrudes from a trench isolation layer on a substrate. The fin comprises a source region, a drain region and a channel region therebetween. A dummy gate strides across the fin and surrounding the channel region. An upper portion of the fin is removed so as to form a hollow channel underneath the dummy gate. A replacement channel layer is in-situ epitaxially grown in the hollow channel.

公开(公告)号：US10388756B2

公开(公告)日：2019-08-20

申请号：US15869087

申请日：2018-01-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Hsing Chen ,  Chun-Yu Chen ,  Chung-Ting Huang ,  Zih-Hsuan Huang ,  Yu-Chien Sung

IPC: H01L29/66 ,  H01L21/3213 ,  H01L29/06 ,  H01L21/033 ,  H01L29/78 ,  H01L27/088

Abstract: A method for fabricating a semiconductor device is disclosed. A fin is formed on a substrate. The fin protrudes from a trench isolation layer on a substrate. The fin comprises a source region, a drain region and a channel region therebetween. A dummy gate strides across the fin and surrounding the channel region. An upper portion of the fin is removed so as to form a hollow channel underneath the dummy gate. A replacement channel layer is in-situ epitaxially grown in the hollow channel.

公开(公告)号：US20180019324A1

公开(公告)日：2018-01-18

申请号：US15590510

申请日：2017-05-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Chen Chan ,  Yi-Fan Li ,  Yen-Hsing Chen ,  Chun-Yu Chen ,  Chung-Ting Huang ,  Zih-Hsuan Huang ,  Ming-Hua Chang ,  Yu-Shu Lin ,  Shu-Yen Chan

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (SiGe) layer epitaxially grown on the top surface and the lateral sidewalls of the fin; and a gate stack formed on the isolation layer and across the fin, wherein the fin and the gate stack respectively extend along a first direction and a second direction. The SiGe layer formed on the top surface has a first thickness, the SiGe layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30.

公开(公告)号：US09006805B2

公开(公告)日：2015-04-14

申请号：US13960816

申请日：2013-08-07

Applicant: United Microelectronics Corp.

Inventor： Chin-I Liao ,  Chun-Yu Chen

IPC: H01L29/41 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes at least two fin-shaped structures, a gate structure, at least two epitaxial structures and a silicon cap. The fin-shaped structures are disposed on a substrate and are covered by the gate structure. The epitaxial structures are disposed at one side of the gate structure and respectively directly contact each fin-shaped structure, wherein the epitaxial structures are spaced apart from each other. The silicon cap simultaneously surrounds the epitaxial structures.

Abstract translation: 半导体器件包括至少两个鳍状结构，栅极结构，至少两个外延结构和硅帽。 鳍状结构设置在基板上并被栅极结构覆盖。 外延结构设置在栅极结构的一侧并且分别直接接触每个鳍状结构，其中外延结构彼此间隔开。 硅帽同时围绕外延结构。

公开(公告)号：US20150041855A1

公开(公告)日：2015-02-12

申请号：US13960816

申请日：2013-08-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-I Liao ,  Chun-Yu Chen

IPC: H01L29/417 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes at least two fin-shaped structures, a gate structure, at least two epitaxial structures and a silicon cap. The fin-shaped structures are disposed on a substrate and are covered by the gate structure. The epitaxial structures are disposed at one side of the gate structure and respectively directly contact each fin-shaped structure, wherein the epitaxial structures are spaced apart from each other. The silicon cap simultaneously surrounds the epitaxial structures.

Abstract translation: 半导体器件包括至少两个鳍状结构，栅极结构，至少两个外延结构和硅帽。 鳍状结构设置在基板上并被栅极结构覆盖。 外延结构设置在栅极结构的一侧并且分别直接接触每个鳍状结构，其中外延结构彼此间隔开。 硅帽同时围绕外延结构。