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    Methods and Apparatus for Scribe Street Probe Pads with Reduced Die Chipping During Wafer Dicing
    13.
    发明申请
    Methods and Apparatus for Scribe Street Probe Pads with Reduced Die Chipping During Wafer Dicing 审中-公开

    公开(公告)号：US20180090454A1

    公开(公告)日：2018-03-29

    申请号：US15820176

    申请日：2017-11-21

    Applicant: Texas Instruments Incorporated

    Inventor： Ricky Alan Jackson ,  Erika Lynn Mazotti ,  Sudtida Lavangkul

    IPC: H01L23/00 ,  H01L23/544 ,  H01L21/66 ,  H01L21/78 ,  H01L23/31

    Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.

    Sloped photoresist edges for defect reduction for metal dry etch processes
    15.
    发明授权
    Sloped photoresist edges for defect reduction for metal dry etch processes 有权

    公开(公告)号：US09716013B2

    公开(公告)日：2017-07-25

    申请号：US14172497

    申请日：2014-02-04

    Applicant: Texas Instruments Incorporated

    Inventor： Elizabeth Costner Stewart ,  Neng Jiang ,  Yung Shan Chang ,  Ricky Alan Jackson

    IPC: H01L21/3213

    CPC classification number: H01L21/32136 ,  H01L21/32139

    Abstract: A method of etching a metal containing layer including a metal including material includes providing a substrate including a top semiconductor surface having the metal containing layer thereon. A photoresist pattern is formed from a photoresist layer on the metal containing layer including forming sloped edge regions of the photoresist layer, wherein the sloped edge regions have an average angle over a full length of the sloped edge regions of from ten (10) to fifty (50) degrees. The metal containing layer is dry etched using the photoresist pattern, wherein the sloped edge regions of the photoresist layer reduce deposition and growth of an etch byproduct including the metal including material into sidewalls of the photoresist layer (metal/polymer sidewall defect) as compared to a conventional vertical (or near-vertical) edge of the photoresist layer.

    MONOLITHIC HUMIDITY SENSOR DEVICES AND METHODS OF MANUFACTURE
    16.
    发明公开
    MONOLITHIC HUMIDITY SENSOR DEVICES AND METHODS OF MANUFACTURE 审中-公开

    公开(公告)号：US20240248059A1

    公开(公告)日：2024-07-25

    申请号：US18597396

    申请日：2024-03-06

    Applicant: Texas Instruments Incorporated

    Inventor： Ricky Alan Jackson ,  Wai Lee

    IPC: G01N27/22

    CPC classification number: G01N27/225 ,  G01N27/226

    Abstract: Monolithic humidity sensor devices, and methods of manufacture. The devices include circuitry on or over a silicon substrate. A primary passivation barrier is formed over the circuitry with conductive vias therethrough; a capacitor, comprising metal fingers with spaces therebetween, is formed above said primary passivation barrier and electrically coupled by the conductive vias to the circuitry. A secondary passivation barrier is formed over the capacitor. A hygroscopic material layer is formed over the secondary passivation barrier, wherein the capacitor is operable to exhibit a capacitance value responsive to moisture present in the hygroscopic material layer and the circuitry is operable to generate a signal responsive to said capacitance value.

    Monolithic humidity sensor devices and methods of manufacture
    17.
    发明授权
    Monolithic humidity sensor devices and methods of manufacture 有权

    公开(公告)号：US11953460B2

    公开(公告)日：2024-04-09

    申请号：US17709692

    申请日：2022-03-31

    Applicant: Texas Instruments Incorporated

    Inventor： Ricky Alan Jackson ,  Wai Lee

    IPC: G01N27/22 ,  H01L23/31 ,  H01L23/64

    CPC classification number: G01N27/225 ,  H01L23/3171 ,  H01L23/642

    Abstract: Monolithic humidity sensor devices, and methods of manufacture. The devices include circuitry on or over a silicon substrate. A primary passivation barrier is formed over the circuitry with conductive vias therethrough; a capacitor, comprising metal fingers with spaces therebetween, is formed above said primary passivation barrier and electrically coupled by the conductive vias to the circuitry. A secondary passivation barrier is formed over the capacitor. A hygroscopic material layer is formed over the secondary passivation barrier, wherein the capacitor is operable to exhibit a capacitance value responsive to moisture present in the hygroscopic material layer and the circuitry is operable to generate a signal responsive to said capacitance value.

    Methods and apparatus for scribe street pads with reduced die chipping during wafer dicing
    20.
    发明授权
    Methods and apparatus for scribe street pads with reduced die chipping during wafer dicing 有权

    公开(公告)号：US10770406B2

    公开(公告)日：2020-09-08

    申请号：US15820176

    申请日：2017-11-21

    Applicant: Texas Instruments Incorporated

    Inventor： Ricky Alan Jackson ,  Erika Lynn Mazotti ,  Sudtida Lavangkul

    IPC: H01L23/00 ,  H01L21/66 ,  H01L21/78 ,  H01L23/58 ,  H01L23/31

    Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.

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