公开(公告)号：US11031320B2

公开(公告)日：2021-06-08

申请号：US16675702

申请日：2019-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung Chen ,  Cheng-Hung Wang ,  Tsung-Lin Lee ,  Shiuan-Jeng Lin ,  Chun-Ming Lin ,  Wen-Chih Chiang

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/58 ,  H01L21/02 ,  H01L29/06 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L21/762

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

公开(公告)号：US20200176359A1

公开(公告)日：2020-06-04

申请号：US16675702

申请日：2019-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung Chen ,  Cheng-Hung Wang ,  Tsung-Lin Lee ,  Shiuan-Jeng Lin ,  Chun-Ming Lin ,  Wen-Chih Chiang

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/58 ,  H01L21/02 ,  H01L21/762 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L29/06

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.