知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.017 seconds)

    Photolithography alignment process for bonded wafers
    12.
    发明授权
    Photolithography alignment process for bonded wafers 有权

    公开(公告)号：US11362038B2

    公开(公告)日：2022-06-14

    申请号：US17062677

    申请日：2020-10-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yeong-Jyh Lin ,  Ching I Li ,  De-Yang Chiou ,  Sz-Fan Chen ,  Han-Jui Hu ,  Ching-Hung Wang ,  Ru-Liang Lee ,  Chung-Yi Yu

    IPC: H01L23/544 ,  H01L21/027 ,  H01L21/683 ,  G03F1/42 ,  G03F1/70 ,  H01L21/66

    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a plurality of upper alignment marks on a semiconductor wafer. A plurality of lower alignment marks is formed on a handle wafer and correspond to the upper alignment marks. The semiconductor wafer is bonded to the handle wafer such that centers of the upper alignment marks are laterally offset from centers of corresponding lower alignment marks. An overlay (OVL) shift is measured between the handle wafer and the semiconductor wafer by detecting the plurality of upper alignment marks and the plurality of lower alignment marks. A photolithography process is performed by a photolithography tool to partially form an integrated circuit (IC) structure over the semiconductor wafer. During the photolithography process the photolithography tool is compensatively aligned according to the OVL shift.

    PHOTOLITHOGRAPHY ALIGNMENT PROCESS FOR BONDED WAFERS
    13.
    发明申请
    PHOTOLITHOGRAPHY ALIGNMENT PROCESS FOR BONDED WAFERS 有权

    公开(公告)号：US20210375781A1

    公开(公告)日：2021-12-02

    申请号：US17062677

    申请日：2020-10-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yeong-Jyh Lin ,  Ching I Li ,  De-Yang Chiou ,  Sz-Fan Chen ,  Han-Jui Hu ,  Ching-Hung Wang ,  Ru-Liang Lee ,  Chung-Yi Yu

    IPC: H01L23/544 ,  H01L21/027 ,  H01L21/683 ,  H01L21/66 ,  G03F1/42 ,  G03F1/70

    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a plurality of upper alignment marks on a semiconductor wafer. A plurality of lower alignment marks is formed on a handle wafer and correspond to the upper alignment marks. The semiconductor wafer is bonded to the handle wafer such that centers of the upper alignment marks are laterally offset from centers of corresponding lower alignment marks. An overlay (OVL) shift is measured between the handle wafer and the semiconductor wafer by detecting the plurality of upper alignment marks and the plurality of lower alignment marks. A photolithography process is performed by a photolithography tool to partially form an integrated circuit (IC) structure over the semiconductor wafer. During the photolithography process the photolithography tool is compensatively aligned according to the OVL shift.

    BACK-SIDE DEEP TRENCH ISOLATION STRUCTURE FOR IMAGE SENSOR
    14.
    发明申请
    BACK-SIDE DEEP TRENCH ISOLATION STRUCTURE FOR IMAGE SENSOR 有权

    公开(公告)号：US20210335861A1

    公开(公告)日：2021-10-28

    申请号：US17017854

    申请日：2020-09-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Hung Cheng ,  Chun-Tsung Kuo ,  Jiech-Fun Lu ,  Min-Ying Tsai ,  Chiao-Chun Hsu ,  Ching I Li

    IPC: H01L27/146

    Abstract: The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensing die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.

    ISOLATION EPITAXIAL BI-LAYER FOR BACKSIDE DEEP TRENCH ISOLATION STRUCTURE IN AN IMAGE SENSOR
    16.
    发明申请
    ISOLATION EPITAXIAL BI-LAYER FOR BACKSIDE DEEP TRENCH ISOLATION STRUCTURE IN AN IMAGE SENSOR 有权

    公开(公告)号：US20220293642A1

    公开(公告)日：2022-09-15

    申请号：US17352919

    申请日：2021-06-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Hung Cheng ,  Ching I Li

    IPC: H01L27/146

    Abstract: In some embodiments, the present disclosure relates to an integrated chip, including a substrate, a first image sensing element and a second image sensing element arranged next to one another over the substrate, the first image sensing element and the second image sensing element having a first doping type, and a backside deep trench isolation (BDTI) structure arranged between the first and second image sensing elements and including a first isolation epitaxial layer setting an outermost sidewall of the BDTI structure and having the first doping type, a second isolation epitaxial layer arranged along inner sidewalls of the first isolation epitaxial layer and having a second doping type different than the first doping type, and an isolation filler structure filling between inner sidewalls of the second isolation epitaxial layer.

Patent Agency Ranking