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11.发明申请公开(公告)号：US20190341110A1
公开(公告)日：2019-11-07
申请号：US16042972
申请日：2018-07-23
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Thuan Vu , Staniey Hong , Anh Ly , Vlpln Tlwarl , Nhan Do
IPC: G11C16/04 , G06N3/08 , H01L29/788 , H01L27/11521
Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.
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12.发明授权
公开(公告)号：US10340010B2
公开(公告)日：2019-07-02
申请号：US15238681
申请日：2016-08-16
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu , Vipin Tiwari , Nhan Do
IPC: G11C16/10 , G11C16/08 , G11C16/14 , G11C16/24 , G11C16/34 , G11C16/26 , G11C16/04 , G11C16/28 , G11C16/32
Abstract: In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to the prior art. In another embodiment of the present invention, two rows in different sectors are selected and one column is selected for a read operation, such that twice as many flash memory cells can be read in a single operation compared to the prior art.
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公开(公告)号：US10325666B2
公开(公告)日：2019-06-18
申请号：US16218398
申请日：2018-12-12
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
IPC: G11C7/00 , G11C16/30 , G11C16/08 , G11C16/04 , G11C16/14 , H01L27/11521 , G11C16/26 , G11C5/14 , G11C16/10 , G11C8/08 , G11C16/16
Abstract: During a program, read, or erase operation of one or more non-volatile flash memory cells in an array of non-volatile flash memory cells, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected non-volatile flash memory cells. The negative voltage is generated by a negative high voltage level shifter using one of several embodiments disclosed herein.
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公开(公告)号：US10216242B2
公开(公告)日：2019-02-26
申请号：US15610612
申请日：2017-05-31
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Thuan Vu , Anh Ly , Hung Quoc Nguyen
IPC: G11C5/14 , G06F1/26 , G06F1/28 , G11C7/20 , G11C16/30 , H03K19/0185 , G11C11/4074
Abstract: A system and method for improved power sequencing within an embedded flash memory device is disclosed. Various power-on sequences and power-down sequences for a plurality of voltage sources are utilized to improve the performance of an embedded flash memory device. The plurality of voltage sources can be used for different purposes within the embedded flash memory device.
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15.发明申请
公开(公告)号：US20180144804A1
公开(公告)日：2018-05-24
申请号：US15873872
申请日：2018-01-17
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu
CPC classification number: G11C16/28 , G11C7/065 , G11C16/0433 , G11C16/14 , G11C16/24
Abstract: The present invention relates to an improved sensing amplifier and related method for use in read operations in flash memory devices. In one embodiment, a voltage offset is induced in the sensing amplifier through the use of capacitors.
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公开(公告)号：US09678553B2
公开(公告)日：2017-06-13
申请号：US15088038
申请日：2016-03-31
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Thuan Vu , Anh Ly , Hung Quoc Nguyen
IPC: G11C5/14 , G06F1/26 , G06F1/28 , G11C7/20 , G11C16/30 , H03K19/0185 , G11C11/4074
CPC classification number: G06F1/266 , G06F1/28 , G11C5/14 , G11C5/143 , G11C5/147 , G11C5/148 , G11C7/20 , G11C11/4074 , G11C16/30 , H03K19/018521
Abstract: The invention relates to a system and method for improved power sequencing within an embedded flash memory device for a plurality of voltage sources. In one embodiment, a power sequence enabling circuit comprises a PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first voltage source. During a power up time period, a voltage output from the first voltage source ramps upward, toward a voltage output from a second voltage source through the PMOS transistor. During a power down period, a voltage from the second voltage source ramps downward toward an intermediate voltage greater than zero volts through the first NMOS transistor.
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17.发明授权System and method to reduce disturbances during programming of flash memory cells 有权减少闪存单元编程过程中的干扰的系统和方法
公开(公告)号：US09418744B2
公开(公告)日：2016-08-16
申请号：US14275362
申请日：2014-05-12
Applicant: Silicon Storage Technology, Inc.
Inventor： Jinho Kim , Anh Ly , Victor Markov
CPC classification number: G11C16/14 , G11C7/02 , G11C8/10 , G11C16/0408 , G11C16/0425 , G11C16/08 , G11C16/3427
Abstract: An improved control gate decoding design may reduce disturbances during the programming of flash memory cells. In one embodiment, a control gate line decoder is coupled to a first control gate line associated with a row of flash memory cells in a first sector and to a second control gate line associated with a row of flash memory cells in a second sector.
Abstract translation: 改进的控制门解码设计可以减少在闪速存储器单元的编程期间的干扰。 在一个实施例中，控制栅极线解码器耦合到与第一扇区中的一行闪存单元相关联的第一控制栅极线和耦合到与第二扇区中的一行闪存单元相关联的第二控制栅极线。
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公开(公告)号：US20240339136A1
公开(公告)日：2024-10-10
申请号：US18206488
申请日：2023-06-06
Applicant: Silicon Storage Technology, Inc.
Inventor： Kha Nguyen , Anh Ly , Hieu Van Tran , Hien Pham , Henry Tran
CPC classification number: G11C7/1039 , G11C7/12
Abstract: Numerous examples are disclosed of a row address decoding scheme. In one example, a memory system comprises m banks of non-volatile memory cells, the m banks respectively comprising n or fewer sectors and the sectors respectively comprising p rows, and a row decoder to receive a row address comprising r bits and to identify (i) a row using the least significant t bits in the r bits, (ii) a bank using the next u least significant bits, and (iii) a sector using the next v least significant bits, where m≤2u, n≤2v, and p≤2t.
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19.发明公开
公开(公告)号：US20240312517A1
公开(公告)日：2024-09-19
申请号：US18419079
申请日：2024-01-22
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Thuan Vu , Stephen Trinh , Stanley Hong , Anh Ly , Steven Lemke , Vipin Tiwari , Nhan Do
CPC classification number: G11C11/54 , G06N3/065 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/3418 , G11C2216/04
Abstract: In one example, a method comprises erasing at the same time a word of non-volatile memory cells in an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal, by turning on an erase gate enable transistor coupled to erase gate terminals of the word of non-volatile memory cells.
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20.发明授权
公开(公告)号：US11586898B2
公开(公告)日：2023-02-21
申请号：US16360733
申请日：2019-03-21
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Thuan Vu , Stephen Trinh , Stanley Hong , Anh Ly
IPC: G06N3/063 , G06N3/08 , G11C16/04 , G11C16/10 , G06F12/0811 , G11C11/4063 , G11C11/54
Abstract: Various embodiments of high voltage generation circuits, high voltage operational amplifiers, adaptive high voltage supplies, adjustable high voltage incrementor, adjustable reference supplies, and reference circuits are disclosed. These circuits optionally can be used for programming a non-volatile memory cell in an analog neural memory to store one of many possible values.
