公开(公告)号：US20220020701A1

公开(公告)日：2022-01-20

申请号：US17203007

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon KO ,  Un-Byoung KANG ,  Jaekyung YOO ,  Teak Hoon LEE

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.

公开(公告)号：US20210366876A1

公开(公告)日：2021-11-25

申请号：US17140241

申请日：2021-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung YOO ,  Jayeon LEE ,  Jae-eun LEE ,  Yeongkwon KO ,  Jin-woo PARK ,  Teak Hoon LEE

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/13 ,  H01L23/498 ,  H01L25/00

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.

公开(公告)号：US20200098719A1

公开(公告)日：2020-03-26

申请号：US16438505

申请日：2019-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Sick PARK ,  Un Byoung KANG ,  Tae Hong MIN ,  Teak Hoon LEE ,  Ji Hwan HWANG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor chip having a first through substrate via (TSV), a second semiconductor chip stacked on the first semiconductor chip and a first adhesive layer disposed between the first semiconductor chip and the second semiconductor chip. The second semiconductor chip includes a second through substrate via connected to the first through substrate via. A side surface of the first adhesive layer is recessed from side surfaces of the first and second semiconductor chips.