公开(公告)号：US11626364B2

公开(公告)日：2023-04-11

申请号：US17113284

申请日：2020-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun Ho Kim ,  Ji Hoon Kim ,  Ha Young Ahn ,  Shang Hoon Seo ,  Seung Yeop Kook ,  Sung Won Jeong

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/13

Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.

公开(公告)号：US10679933B2

公开(公告)日：2020-06-09

申请号：US16598046

申请日：2019-10-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun Ho Kim ,  Ji Hoon Kim ,  Ha Young Ahn ,  Shang Hoon Seo ,  Seung Yeop Kook ,  Sung Won Jeong

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/13

Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.

公开(公告)号：US10461008B2

公开(公告)日：2019-10-29

申请号：US15205483

申请日：2016-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Won Jeong ,  Ji Hoon Kim ,  Sun Ho Kim ,  Shang Hoon Seo ,  Seung Yeop Kook ,  Christian Romero

IPC: H01L23/31 ,  H01L23/48 ,  H01L25/10 ,  H01L23/00 ,  H01L23/29 ,  H01L23/552

Abstract: An electronic component package includes a wiring part including an insulating layer, a conductive pattern formed on the insulating layer, and a conductive via connected to the conductive pattern through the insulating layer, an electronic component disposed on the wiring part, a frame disposed on the wiring part and having a component disposition region defined by an inner wall of the frame surrounding the electronic component, and an encapsulant filling at least a portion of the component disposition region. A portion of the inner wall of the frame forms a protrusion protruding toward the electronic component.