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    SYSTEMS AND METHODS FOR PREFETCHING DATA VIA A HOST-ACCESSIBLE PREFETCHER QUEUE
    11.
    发明申请
    SYSTEMS AND METHODS FOR PREFETCHING DATA VIA A HOST-ACCESSIBLE PREFETCHER QUEUE 有权

    公开(公告)号：US20240378153A1

    公开(公告)日：2024-11-14

    申请号：US18231122

    申请日：2023-08-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tong Zhang ,  Zongwang Li ,  Da Zhang ,  Rekha Pitchumani ,  Yang Seok Ki

    IPC: G06F12/0862

    Abstract: Systems and methods for prefetching data are disclosed. A processor executes a first command for moving first data stored in a storage device. Based on the first command, the processor stores, into a first queue of the storage device, a first address associated with the first data. The storage device further retrieves the first address from the first queue, retrieves the first data from the first storage medium based on the first address, and stores the first data to the second storage medium. In some embodiments, a process for prefetch optimization is also disclosed. A processor identifies a value for prefetching data. The processor runs an application, measures performance of the application, modifies the value based on the performance, and determines that the performance satisfies a criterion.

    Enhanced SSD reliability
    12.
    发明授权
    Enhanced SSD reliability 有权

    公开(公告)号：US12050811B2

    公开(公告)日：2024-07-30

    申请号：US18198256

    申请日：2023-05-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yang Seok Ki ,  Rekha Pitchumani

    IPC: G06F3/06 ,  G06F11/10

    CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0673 ,  G06F11/1068

    Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include an interface to receive read and write requests from an application on a host. Storage, including at least one chip, may store data. An SSD controller may process the read and write requests from the application. A configuration module may configure the SSD. Storage may include a reliability table which may include entries specifying configurations of the SSD and reliabilities for those configurations.

    Systems and methods for a redundant array of independent disks (RAID) using a decoder in cache coherent interconnect storage devices
    13.
    发明授权
    Systems and methods for a redundant array of independent disks (RAID) using a decoder in cache coherent interconnect storage devices 有权

    公开(公告)号：US11995316B2

    公开(公告)日：2024-05-28

    申请号：US17885520

    申请日：2022-08-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tong Zhang ,  Heekwon Park ,  Rekha Pitchumani ,  Yang Seok Ki

    IPC: G06F3/06

    CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0689

    Abstract: A system is disclosed. The system may include a processor that may issue a byte level protocol request including a byte address. The system may also include a first storage device and a second storage device. The first storage device and the second storage device may support a cache coherent interconnect protocol, the cache coherent interconnect protocol including a block level protocol and a byte level protocol. The first storage device and the second storage device are included in a redundant array of independent disks (RAID). The first storage device may include a first address range, and the second storage device may include a second address range. The second storage device may provide a RAID address range associated with the first address range and the second address range. A decoder associated with the second storage device may be configured to receive the request from the processor. The decoder may determine that the byte address in the RAID address range is associated with a target address range.

    Systems, methods, and devices for accelerators with virtualization and tiered memory
    14.
    发明授权
    Systems, methods, and devices for accelerators with virtualization and tiered memory 有权

    公开(公告)号：US11914903B2

    公开(公告)日：2024-02-27

    申请号：US17497882

    申请日：2021-10-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yang Seok Ki ,  Krishna T. Malladi ,  Rekha Pitchumani

    IPC: G06F3/06

    CPC classification number: G06F3/0664 ,  G06F3/0604 ,  G06F3/0679

    Abstract: A device may include an interconnect interface, a memory system including one or more first type memory devices to receive first data, one or more second type memory devices to receive second data, and an accelerator configured to perform an operation using the first data and the second data. The memory system may further include a cache configured to cache the second data for the one or more second type memory devices. A device may include an interconnect interface, a memory system coupled to the interconnect interface to receive data, an accelerator coupled to the memory system, and virtualization logic configured to partition one or more resources of the accelerator into one or more virtual accelerators, wherein a first one of the one or more virtual accelerators may be configured to perform a first operation on a first portion of the data.

    Error correction on length-compatible polar codes for memory systems
    15.
    发明授权
    Error correction on length-compatible polar codes for memory systems 有权

    公开(公告)号：US11513897B2

    公开(公告)日：2022-11-29

    申请号：US17203745

    申请日：2021-03-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Wei Wu ,  Rekha Pitchumani ,  Zongwang Li

    IPC: G06F11/10 ,  G06F11/00 ,  H03M13/13 ,  G06F17/16

    Abstract: Inventive aspects include a polar code encoding system, which includes a partitioning unit to receive and partition input data into partitioned input data units. Encoders encode the partitioned input data units, and generate encoded partitioned input data units. Multiplier units perform matrix multiplication on the partitioned input data units and generator matrices, and generate matrix products. Adder units perform matrix addition on the encoded partitioned input data units and the matrix products. A combining unit combines outputs of the encoders into a target code word X. The target code word X may be a length-N code word X, where N=N1+N2+ . . . +Nm, where each of N1, N2, through Nm are a power of two (2).

    Offloaded device-driven erasure coding
    16.
    发明授权
    Offloaded device-driven erasure coding 有权

    公开(公告)号：US11210002B2

    公开(公告)日：2021-12-28

    申请号：US15930422

    申请日：2020-05-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Rekha Pitchumani ,  Yang Seok Ki

    IPC: G06F13/00 ,  G06F3/06 ,  G06F11/14 ,  G06F11/20

    Abstract: A method for storing data may include receiving user data at a group of storage devices, wherein the storage devices are interconnected, erasure coding the user data into redundancy blocks at the group of storage devices, and storing the redundancy blocks on at least two of the storage devices. The erasure encoding may be distributed among at least two of the storage devices. The redundancy blocks may be arranged in reliability groups. The redundancy blocks may be grouped by the storage devices independently of the partitioning of the user data by the user. The method may further include recovering data based on redundancy blocks. A storage device may include a storage medium, a network interface configured to communicate with one or more other storage devices, and a storage processing unit configured to erasure code user data into redundancy blocks cooperatively with the one or more other storage devices.

    FPGA acceleration system for MSR codes
    17.
    发明授权
    FPGA acceleration system for MSR codes 有权

    公开(公告)号：US10929227B2

    公开(公告)日：2021-02-23

    申请号：US16271777

    申请日：2019-02-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mian Qin ,  Joo Hwan Lee ,  Rekha Pitchumani ,  Yang Seok Ki

    IPC: G06F11/10 ,  G06F13/28

    Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.

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