公开(公告)号：US20140331021A1

公开(公告)日：2014-11-06

申请号：US14270795

申请日：2014-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Young KIM

IPC: G06F13/16

CPC classification number: G06F13/1689 ,  G06F13/161 ,  G06F13/1626

Abstract: A memory control apparatus that minimizes memory bank collisions by rescheduling memory requests. The memory control apparatus includes a scheduler configured to, in response to at least two memory requests existing in a current cycle, schedule a plurality of elements included in the at least two memory requests based on information about memory banks determined for the plurality of elements; and a request generator configured to, in response to the scheduling of the plurality of elements by the scheduler, generate a scheduled memory request for the current cycle using at least one element in the at least two memory requests in order to prevent a memory bank collision.

Abstract translation: 一种通过重新安排存储器请求来最小化存储体冲突的存储器控​​制装置。 存储器控制装置包括调度器，其被配置为响应于当前周期中存在的至少两个存储器请求，基于关于为多个元素确定的存储体的信息调度包括在所述至少两个存储器请求中的多个元素; 以及请求生成器，被配置为响应于所述调度器对所述多个元素的调度，使用所述至少两个存储器请求中的至少一个元素来生成所述当前周期的调度存储器请求，以便防止存储器组碰撞 。