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    Adaptive matrix multiplication accelerator for machine learning and deep learning applications
    11.
    发明授权
    Adaptive matrix multiplication accelerator for machine learning and deep learning applications 有权

    公开(公告)号：US12153646B2

    公开(公告)日：2024-11-26

    申请号：US17967733

    申请日：2022-10-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongyan Jiang ,  Dimin Niu ,  Hongzhong Zheng

    IPC: G06F17/16 ,  G06F9/38 ,  G06F9/50

    Abstract: An adaptive matrix multiplier. In some embodiments, the matrix multiplier includes a first multiplying unit a second multiplying unit, a memory load circuit, and an outer buffer circuit. The first multiplying unit includes a first inner buffer circuit and a second inner buffer circuit, and the second multiplying unit includes a first inner buffer circuit and a second inner buffer circuit. The memory load circuit is configured to load data from memory, in a single burst of a burst memory access mode, into the first inner buffer circuit of the first multiplying unit; and into the first inner buffer circuit of the second multiplying unit.

    Adaptive matrix multiplication accelerator for machine learning and deep learning applications
    12.
    发明授权
    Adaptive matrix multiplication accelerator for machine learning and deep learning applications 有权

    公开(公告)号：US12141227B2

    公开(公告)日：2024-11-12

    申请号：US16942570

    申请日：2020-07-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongyan Jiang ,  Dimin Niu ,  Hongzhong Zheng

    IPC: G06F17/16 ,  G06F9/38 ,  G06F9/50

    Abstract: An adaptive matrix multiplier. In some embodiments, the matrix multiplier includes a first multiplying unit a second multiplying unit, a memory load circuit, and an outer buffer circuit. The first multiplying unit includes a first inner buffer circuit and a second inner buffer circuit, and the second multiplying unit includes a first inner buffer circuit and a second inner buffer circuit. The memory load circuit is configured to load data from memory, in a single burst of a burst memory access mode, into the first inner buffer circuit of the first multiplying unit; and into the first inner buffer circuit of the second multiplying unit.

    Effective transaction table with page bitmap
    15.
    发明授权
    Effective transaction table with page bitmap 有权

    公开(公告)号：US12282654B2

    公开(公告)日：2025-04-22

    申请号：US17480061

    申请日：2021-09-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongyan Jiang ,  Hongzhong Zheng

    IPC: G06F3/06 ,  G06F9/46 ,  G06F12/0831 ,  G06F12/1009

    Abstract: A transaction manager for use with memory is described. The transaction manager can include a write data buffer to store outstanding write requests, a read data multiplexer to select between data read from the memory and the write data buffer, a command queue and a priority queue to store requests for the memory, and a transaction table to track outstanding write requests, each write request associated with a state that is Invalid, Modified, or Forwarded.

    Scalable architecture enabling large memory system for in-memory computations
    16.
    发明授权
    Scalable architecture enabling large memory system for in-memory computations 有权

    公开(公告)号：US12099736B2

    公开(公告)日：2024-09-24

    申请号：US16828930

    申请日：2020-03-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongyan Jiang ,  Qiang Peng ,  Hongzhong Zheng

    IPC: G06F3/06

    CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0671

    Abstract: A memory system provides deduplication of user data in the physical memory space of the system for user data that is duplicated in the virtual memory space of a host system. A transaction manager (TM) uses a transaction table to maintain data coherency and data concurrency for the virtual memory space. A write data engine manager (WDEM) uses an outstanding bucket number and command queues to maintain data coherency and data concurrency for the physical memory space. The WDEM receives data write requests from the TM and sends a corresponding write command to a selected command queue. A write data engine responds to a write command in a command queue by storing the data in an overflow memory region if the data is not duplicated in the virtual memory space, or by incrementing a reference counter for the data if the data is duplicated in the virtual memory space.

    ADAPTIVE MATRIX MULTIPLICATION ACCELERATOR FOR MACHINE LEARNING AND DEEP LEARNING APPLICATIONS
    17.
    发明申请
    ADAPTIVE MATRIX MULTIPLICATION ACCELERATOR FOR MACHINE LEARNING AND DEEP LEARNING APPLICATIONS 审中-公开

    公开(公告)号：US20200272479A1

    公开(公告)日：2020-08-27

    申请号：US16407064

    申请日：2019-05-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongyan Jiang ,  Dimin Niu ,  Hongzhong Zheng

    IPC: G06F9/38 ,  G06F9/50 ,  G06F17/16

    Abstract: An adaptive matrix multiplier. In some embodiments, the matrix multiplier includes a first multiplying unit a second multiplying unit, a memory load circuit, and an outer buffer circuit. The first multiplying unit includes a first inner buffer circuit and a second inner buffer circuit, and the second multiplying unit includes a first inner buffer circuit and a second inner buffer circuit. The memory load circuit is configured to load data from memory, in a single burst of a burst memory access mode, into the first inner buffer circuit of the first multiplying unit; and into the first inner buffer circuit of the second multiplying unit.

    Dedupe DRAM cache
    18.
    发明授权
    Dedupe DRAM cache 有权

    公开(公告)号：US10705969B2

    公开(公告)日：2020-07-07

    申请号：US15934940

    申请日：2018-03-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu Tien Chang ,  Andrew Chang ,  Dongyan Jiang ,  Hongzhong Zheng

    IPC: G06F12/08 ,  G06F12/0891 ,  G06F3/06

    Abstract: A dedupable cache is disclosed. The dedupable cache may include cache memory including both a dedupable read cache and a non-dedupable write buffer. The dedupable cache may also include a deduplication engine to manage reads from and writes to the dedupable read cache, and may return a write status signal indicating whether a write to the dedupable read cache was successful or not. The dedupable cache may also include a cache controller, which may include: a cache hit/miss check to determine whether an address in a request may be found in the dedupable read cache; a hit block to manage data accesses when the requested data may be found in the dedupable read cache; a miss block to manage data accesses when the requested data is not found in the dedupable read cache; and a history storage to store information about accesses to the data in the dedupable read cache.

    Method and apparatus for enabling larger memory capacity than physical memory size
    19.
    发明授权
    Method and apparatus for enabling larger memory capacity than physical memory size 有权

    公开(公告)号：US10678704B2

    公开(公告)日：2020-06-09

    申请号：US15476757

    申请日：2017-03-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongyan Jiang ,  Changhui Lin ,  Krishna Malladi ,  Jongmin Gim ,  Hongzhong Zheng

    IPC: G06F12/1018 ,  G06F3/06 ,  G06F12/0864

    Abstract: A method of retrieving data stored in a memory associated with a dedupe module is provided. The method includes: identifying a logical address of the data; identifying a physical line ID of the data in accordance with the logical address by looking up at least a portion of the logical address in a translation table; locating a respective physical line, the respective physical line corresponding to the PLID; and retrieving the data from the respective physical line, the retrieving including copying a respective hash cylinder to the read cache, the respective hash cylinder including: a respective hash bucket, the respective hash bucket including the respective physical line; and a respective reference counter bucket, the respective reference counter bucket including a respective reference counter associated with the respective physical line.

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