公开(公告)号：US09966021B2

公开(公告)日：2018-05-08

申请号：US15179080

申请日：2016-06-10

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Woonyong Kim ,  Kyeongseok Lee ,  Jaehyun Koh ,  Sung-Jun Kim ,  Jeong-Hyun Kim ,  Sungsoo Choi

IPC: G09G5/10 ,  G09G3/36

CPC classification number: G09G3/3607 ,  G09G3/3611 ,  G09G3/3614 ,  G09G3/3685 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/08 ,  G09G2320/0223 ,  G09G2320/0242

Abstract: A display apparatus includes a display panel, a timing controller and a data driver. The display panel includes a data line and first and second pixels connected to the data line. The timing controller generates a data signal and a data kickback control signal in response to input image data. The data driver generates first and second data voltages in response to the data signal, generates a data kickback signal in response to the data kickback control signal, processes the data voltages and the data kickback signal, and outputs the first data voltage to the data line during a first duration, the second data voltage to the data line during a second duration, and a first kickback data voltage to the data line during a first data kickback duration. The first data kickback duration is between the first and second durations.

公开(公告)号：US09779675B2

公开(公告)日：2017-10-03

申请号：US14563200

申请日：2014-12-08

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Min-Young Park ,  Jeong-Doo Lee ,  Sung-Jun Kim ,  Yun-Mi Kim ,  Kyung-Hwa Lim ,  Ki-Hyun Pyun

IPC: G09G3/36

CPC classification number: G09G3/3614 ,  G09G3/3611 ,  G09G2310/08 ,  G09G2320/0233

Abstract: A display device includes a display panel, a variable gate clock generator and a gate driver. The display panel includes a plurality of pixels coupled to a plurality of data lines and a plurality of gate lines, respectively. The variable gate clock generator generates a first variable gate clock signal and a second variable gate clock signal having respective duty ratios that are varied depending on a brightness of a frame image. The gate driver generates a plurality of gate driving signals for driving the gate lines in response to the first and second variable gate clock signals.