公开(公告)号：US20230135708A1

公开(公告)日：2023-05-04

申请号：US17965243

申请日：2022-10-13

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar VERMA

IPC: G06F3/06

Abstract: A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A first word line signal is applied to a selected one of the first word lines to read less significant bits from the first sub-array, and a mathematical operation is performed on the read less significant bits to produce modified less significant bits that are written back to the first sub-array. If the read less significant bits are saturated, a second word line signal is applied to a selected one of the second word lines to read more significant bits from the second sub-array, and a mathematical operation is performed on the read more significant bits to produce modified more significant bits that are written back to the second sub-array.

公开(公告)号：US20230050783A1

公开(公告)日：2023-02-16

申请号：US17861384

申请日：2022-07-11

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar VERMA ,  Harsh RAWAT

IPC: G11C11/419 ,  G11C11/418

Abstract: A memory array includes memory cells forming a data word location accessed in response to a word line signal. A data sensing circuit configured to sense data on bit lines associated with the memory cells. The sensed data corresponds to a current data word stored at the data word location. A data latching circuit latches the sensed data for the current data word from the data sensing circuit. A data modification circuit then performs a mathematical modify operation on the current data word to generate a modified data word. The modified data word is then applied by a data writing circuit to the bit lines for writing back to the memory cells of the memory array at the data word location. The operations are advantageously performed within a single clock cycle.

公开(公告)号：US20230018420A1

公开(公告)日：2023-01-19

申请号：US17853026

申请日：2022-06-29

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar VERMA ,  Promod KUMAR ,  Harsh RAWAT

IPC: G11C8/20 ,  G11C11/418

Abstract: A method of corrupting contents of a memory array includes asserting a signal at a reset node to thereby cause starving of current supply to the memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted. For each desired column, a logic state of its bit line and complementary bit line are forced to a same logic state. Each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted is simultaneously asserted, and then simultaneously deasserted to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.