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    SSD architecture for FPGA based acceleration
    13.
    发明授权
    SSD architecture for FPGA based acceleration 有权

    公开(公告)号：US10585843B2

    公开(公告)日：2020-03-10

    申请号：US16124179

    申请日：2018-09-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ramdas P. Kachare ,  Fred Worley ,  Harry Rogers ,  Wentao Wu ,  Nagarajan Subramaniyan

    IPC: G06F13/16 ,  G06F13/42 ,  G06F9/445 ,  G06F13/40

    Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream port enables communication with the processor; a downstream port enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a physical function (PF) to expose the storage device, a second function to expose the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. A downstream filter associated with the downstream port may intercept an acceleration instruction associated with a downstream Filter Address Range (FAR) received from the storage device and deliver the acceleration instruction to the APM-F, the acceleration instruction being. An upstream filter associated with the upstream port may intercept an acceleration instruction received from the processor and deliver the second acceleration instruction to the APM-F. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus. The acceleration module may support performing the acceleration instruction on the application data on the storage device for the application program without loading the application data into the memory.

    MULTI-PROTOCOL IO INFRASTRUCTURE FOR A FLEXIBLE STORAGE PLATFORM
    16.
    发明申请
    MULTI-PROTOCOL IO INFRASTRUCTURE FOR A FLEXIBLE STORAGE PLATFORM 审中-公开
    用于灵活存储平台的多协议IO基础设施

    公开(公告)号：US20160328347A1

    公开(公告)日：2016-11-10

    申请号：US15090409

    申请日：2016-04-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Fred Worley ,  Harry Rogers ,  Sreenivas Krishnan ,  Zhan Ping ,  Michael Scriber

    IPC: G06F13/38 ,  G06F13/40 ,  G06F13/42

    CPC classification number: G06F13/385 ,  G06F13/4022 ,  G06F13/4282

    Abstract: A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.

    Abstract translation: 灵活的存储系统。 存储主板在合适的连接器上容纳在主机总线接口和存储接口之间提供协议转换的存储适配器电路，并且提供路由以容纳可连接到存储适配器电路的多个大容量存储设备 通过存储主板。 可以用支持不同主机接口或不同存储接口的电路来替换存储适配器电路。

    SSD architecture for FPGA based acceleration
    19.
    发明授权
    SSD architecture for FPGA based acceleration 有权

    公开(公告)号：US11100017B2

    公开(公告)日：2021-08-24

    申请号：US16752612

    申请日：2020-01-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ramdas P. Kachare ,  Fred Worley ,  Harry Rogers ,  Wentao Wu ,  Nagarajan Subramaniyan

    IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

    Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream interface enables communication with the processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus. The acceleration module may support performing the acceleration instruction on the application data on the storage device for the application program without loading the application data into the memory.

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