公开(公告)号：US20180150125A1

公开(公告)日：2018-05-31

申请号：US15799601

申请日：2017-10-31

Applicant: QUALCOMM Incorporated

Inventor： Sandip HomChaudhuri ,  Douglas Dahlby ,  Murali Krishna ,  Harinder Singh ,  Ravi Konda ,  BalaSubrahmanyam Chintamneedi

IPC: G06F1/32 ,  G06N99/00 ,  G06F12/128 ,  G06F12/0862

CPC classification number: G06F1/3275 ,  G06F1/3287 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4418 ,  G06F12/0215 ,  G06F12/0862 ,  G06F12/1009 ,  G06F12/123 ,  G06F12/128 ,  G06F13/4282 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/65 ,  G06F2212/654 ,  G06F2213/0026 ,  G06N3/0445 ,  G06N3/084 ,  G06N7/005 ,  G06N20/00 ,  H04W52/028 ,  Y02D10/44 ,  Y02D70/00 ,  Y02D70/10 ,  Y02D70/1262 ,  Y02D70/14 ,  Y02D70/142 ,  Y02D70/146 ,  Y02D70/26

Abstract: The disclosure relates to minimizing power consumption of a WiFi system-on-chip (SOC) during idle periods. The disclosed architecture includes memory banks for the WiFi SoC's embedded processor that can be independently powered on/off and a Memory Management Unit (MMU) to translate virtual addresses to physical addresses and generate exceptions to process accesses to virtual addresses without a corresponding physical address. The architecture can implement a demand paging scheme whereby a MMU fault from an access to code/data not within the embedded memory causes the processor to fetch the code/data from an off-chip secondary memory. To minimize page faults, the architecture stores WiFi client code/data within the embedded processor's memory that is repeatedly accessed with small periodicity or where there is an intolerance for delays of accessing the code/data.

公开(公告)号：US20180150124A1

公开(公告)日：2018-05-31

申请号：US15799481

申请日：2017-10-31

Applicant: QUALCOMM Incorporated

Inventor： Sandip HomChaudhuri ,  Douglas Dahlby ,  Murali Krishna ,  Harinder Singh ,  Ravi Konda ,  BalaSubrahmanyam Chintamneedi

IPC: G06F1/32 ,  G06F12/02 ,  G06F12/1009 ,  G06F13/42 ,  G06F9/44 ,  G06F12/123

CPC classification number: G06F1/3275 ,  G06F1/3287 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4418 ,  G06F12/0215 ,  G06F12/0862 ,  G06F12/1009 ,  G06F12/123 ,  G06F12/128 ,  G06F13/4282 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/65 ,  G06F2212/654 ,  G06F2213/0026 ,  G06N3/0445 ,  G06N3/084 ,  G06N7/005 ,  G06N20/00 ,  H04W52/028 ,  Y02D10/44 ,  Y02D70/00 ,  Y02D70/10 ,  Y02D70/1262 ,  Y02D70/14 ,  Y02D70/142 ,  Y02D70/146 ,  Y02D70/26

Abstract: The disclosure relates to minimizing power consumption of a WiFi system-on-chip (SOC) during idle periods. The disclosed architecture includes memory banks for the WiFi SoC's embedded processor that can be independently powered on/off and a Memory Management Unit (MMU) to translate virtual addresses to physical addresses and generate exceptions to process accesses to virtual addresses without a corresponding physical address. The architecture can implement a demand paging scheme whereby a MMU fault from an access to code/data not within the embedded memory causes the processor to fetch the code/data from an off-chip secondary memory. To minimize page faults, the architecture stores WiFi client code/data within the embedded processor's memory that is repeatedly accessed with a short periodicity or where there is an intolerance for delays of accessing the code/data.

公开(公告)号：US20180150123A1

公开(公告)日：2018-05-31

申请号：US15798778

申请日：2017-10-31

Applicant: QUALCOMM Incorporated

Inventor： Sandip HomChaudhuri ,  Douglas Dahlby ,  Murali Krishna ,  Harinder Singh ,  Ravi Konda ,  BalaSubrahmanyam Chintamneedi

IPC: G06F1/32 ,  G06F12/1009 ,  G06F13/42 ,  G06F9/44

Abstract: The disclosure relates to minimizing power consumption of a WiFi system-on-chip (SOC) during idle periods. The disclosed architecture includes memory banks for the WiFi SoC's embedded processor that can be independently powered on/off and a Memory Management Unit (MMU) to translate virtual addresses to physical addresses and generate exceptions to process accesses to virtual addresses without a corresponding physical address. The architecture can implement a demand paging scheme whereby a MMU fault from an access to code/data not within the embedded memory causes the processor to fetch the code/data from an off-chip secondary memory. To minimize page faults, the architecture stores WiFi client code/data within the embedded processor's memory that is repeatedly accessed with a short periodicity or where there is an intolerance for delays of accessing the code/data.