公开(公告)号：US20220291900A1

公开(公告)日：2022-09-15

申请号：US17197359

申请日：2021-03-10

Applicant: QUALCOMM Incorporated

Inventor： Seyed Arash MIRHAJ ,  Ankit SRIVASTAVA ,  Sameer WADHWA

IPC: G06F7/544

Abstract: Various embodiments include devices and methods for a multi-bit multiplier-accumulator (MAC). Some embodiments may include an analog adder having a first adder capacitor. The first adder capacitor may add a plurality of single-bit MAC outputs by receiving the plurality of single-bit MAC outputs from a plurality of single-bit MACs, and storing the plurality of single-bit MAC outputs. In some embodiments, the analog adder may output a multi-bit MAC output based on addition of the stored plurality of single-bit MAC outputs.

公开(公告)号：US20140177850A1

公开(公告)日：2014-06-26

申请号：US13723170

申请日：2012-12-20

Applicant: QUALCOMM INCORPORATED

Inventor： Xiaohong QUAN ,  Peter J. SHAH ,  Ankit SRIVASTAVA ,  Guoqing MIAO

IPC: H04R3/00

CPC classification number: H04R3/007 ,  H04R29/001

Abstract: Techniques for sensing the resistance of a load. In an aspect, a sense resistor is provided in series with the load. Each terminal of the sense resistor is alternately coupled via switches to a sense amplifier. A second input of the sense resistor is coupled to a terminal of the load. The voltage drop across the load and the voltage drop across the load plus sense resistor are alternatively measured. These voltage drops may be digitized and used to compute a resistance of the load using, e.g., a digital processor.

Abstract translation: 用于感测负载电阻的技术。 在一方面，与负载串联提供感测电阻器。 检测电阻器的每个端子通过开关交替耦合到读出放大器。 检测电阻的第二输入耦合到负载的端子。 交替地测量负载上的电压降和负载+检测电阻两端的电压降。 这些电压降可以被数字化并且用于使用例如数字处理器来计算负载的电阻。